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Message-Id: <20220902233543.390890-3-helgaas@kernel.org>
Date: Fri, 2 Sep 2022 18:35:42 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Kai-Heng Feng <kai.heng.feng@...onical.com>,
Rajvi Jingar <rajvi.jingar@...ux.intel.com>,
"Rafael J . Wysocki" <rafael@...nel.org>
Cc: Koba Ko <koba.ko@...onical.com>,
Mika Westerberg <mika.westerberg@...ux.intel.com>,
"David E . Box" <david.e.box@...ux.intel.com>,
Sathyanarayanan Kuppuswamy
<sathyanarayanan.kuppuswamy@...ux.intel.com>,
linux-pci@...r.kernel.org, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, Bjorn Helgaas <bhelgaas@...gle.com>
Subject: [PATCH v2 2/3] PCI/PTM: Implement pci_enable_ptm() for Root Ports, Switch Upstream Ports
From: Bjorn Helgaas <bhelgaas@...gle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@...gle.com>
---
drivers/pci/pcie/ptm.c | 34 +++++++++++++++++++++++++++-------
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c
index b6a417247ce3..ad283818f37b 100644
--- a/drivers/pci/pcie/ptm.c
+++ b/drivers/pci/pcie/ptm.c
@@ -167,11 +167,11 @@ int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
if (!pos)
return -EINVAL;
- pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
- if (!(cap & PCI_PTM_CAP_REQ))
- return -EINVAL;
-
/*
+ * Root Ports and Switch Upstream Ports have been configured
+ * by pci_ptm_init(), so preserve their PCI_PTM_CTRL_ROOT and
+ * granularity.
+ *
* For a PCIe Endpoint, PTM is only useful if the endpoint can
* issue PTM requests to upstream devices that have PTM enabled.
*
@@ -179,19 +179,39 @@ int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
* device, so there must be some implementation-specific way to
* associate the endpoint with a time source.
*/
- if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) {
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
+ pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM) {
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM) {
+ ups = pci_upstream_bridge(dev);
+ if (!ups || !ups->ptm_enabled)
+ return -EINVAL;
+ }
+
+ pci_read_config_dword(dev, pos + PCI_PTM_CTRL, &ctrl);
+ ctrl |= PCI_PTM_CTRL_ENABLE;
+ } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) {
+ pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
+ if (!(cap & PCI_PTM_CAP_REQ))
+ return -EINVAL;
+
ups = pci_upstream_bridge(dev);
if (!ups || !ups->ptm_enabled)
return -EINVAL;
dev->ptm_granularity = ups->ptm_granularity;
+ ctrl = PCI_PTM_CTRL_ENABLE;
+ ctrl |= dev->ptm_granularity << 8;
} else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
+ pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
+ if (!(cap & PCI_PTM_CAP_REQ))
+ return -EINVAL;
+
dev->ptm_granularity = 0;
+ ctrl = PCI_PTM_CTRL_ENABLE;
+ ctrl |= dev->ptm_granularity << 8;
} else
return -EINVAL;
- ctrl = PCI_PTM_CTRL_ENABLE;
- ctrl |= dev->ptm_granularity << 8;
pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
dev->ptm_enabled = 1;
--
2.25.1
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