linux-kernel - Re: [PATCH 00/15] Introduce Architectural LBR for vPMU

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Date:   Fri, 2 Sep 2022 11:44:22 +0800
From:   "Yang, Weijiang" <weijiang.yang@...el.com>
To:     Sean Christopherson <seanjc@...gle.com>
CC:     "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "like.xu.linux@...il.com" <like.xu.linux@...il.com>,
        "kan.liang@...ux.intel.com" <kan.liang@...ux.intel.com>,
        "Wang, Wei W" <wei.w.wang@...el.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 00/15] Introduce Architectural LBR for vPMU


On 9/1/2022 10:23 PM, Sean Christopherson wrote:
> On Wed, Aug 31, 2022, Yang Weijiang wrote:
>> The old patch series was queued in KVM/queue for a while and finally
>> moved to below branch after Paolo's refactor. This new patch set is
>> built on top of Paolo's work + some fixes, it's tested on legacy platform
> Please elaborate on what was broken, i.e. why this was de-queued, as well as on
> what was fixed an dhow.  That will help bring me up to speed and expedite review.
Thanks Sean!
The de-queued reason I read from community is, the PEBS and Arch-LBR 
patches broke
selftest/KUTs due to host-initiated 0 writes to PMU msrs. Paolo tried to 
fix it but you
didn't agree on the solution. Plus your comments below:


On 6/1/2022 4:54 PM, Paolo Bonzini wrote:
 > On 5/31/22 20:37, Sean Christopherson wrote:
 >> Can we just punt this out of kvm/queue until its been properly reviewed?
 > Yes, I agree.  I have started making some changes and pushed the
 > result to kvm/arch-lbr-for-weijiang.

What are fixed in this series:

1.  An missing of -1: if ((entry->eax & 0xff) != (1 << (depth_bit - 1)))

2.  Removed exit bit check in  cpu_has_vmx_arch_lbr(void), moved it to 
setup_vmcs_config().

3.  A redundant check kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR) in 
kvm_check_cpuid().

4.  KUT/selftest failures due to lack of MSR_ARCH_LBR_CTL and 
MSR_ARCH_LBR_DEPTH in kvm_set_msr_common() before validate pmu msrs.

5.  Calltrace in L1 when L1 tried to vmcs_write64(GUEST_IA32_LBR_CTL, 0) 
in vmx_vcpu_reset(), use cpu_has_vmx_arch_lbr() instead.

6.  Removed VM_ENTRY_LOAD_IA32_LBR_CTL and VM_EXIT_CLEAR_IA32_LBR_CTL 
from exec_control in nested case.