linux-kernel - Re: [PATCH v2 1/2] gpio: Add gpio latch driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <CAHp75VchGZV-cPzZnDRBmd_+jEiRap7oA2oFz6w8dBw=7LNtbQ@mail.gmail.com>
Date:   Fri, 2 Sep 2022 10:20:08 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Sascha Hauer <s.hauer@...gutronix.de>
Cc:     "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Geert Uytterhoeven <geert@...ux-m68k.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Bartosz Golaszewski <brgl@...ev.pl>,
        Sascha Hauer <kernel@...gutronix.de>
Subject: Re: [PATCH v2 1/2] gpio: Add gpio latch driver

On Fri, Sep 2, 2022 at 10:16 AM Sascha Hauer <s.hauer@...gutronix.de> wrote:
> On Fri, Sep 02, 2022 at 09:42:21AM +0300, Andy Shevchenko wrote:
> > On Wed, Aug 31, 2022 at 9:02 AM Sascha Hauer <s.hauer@...gutronix.de> wrote:
> > >
> > > This driver implements a GPIO multiplexer based on latches connected to
> > > other GPIOs. A set of data GPIOs is connected to the data input of
> > > multiple latches. The clock input of each latch is driven by another
> > > set of GPIOs. With two 8-bit latches 10 GPIOs can be multiplexed into
> > > 16 GPIOs. GPOs might be a better term as in fact the multiplexed pins
> > > are output only.
> >
> > So, this is for only one type of latches, now I'm wondering why
> > gpio-74xx-mmio can't cover this case (with probably small
> > modifications to the code)?
>
> gpio-74xx-mmio is about latches connected to a parallel bus. You can
> access the GPIOs by doing readl/writel operations. The latches are
> driven by the bus logic and likely an additional address decoder.
>
> What I have here instead is a latch fully driven by GPIOs.

But this reminds me of some kind of gpio-aggregator with a specific
layer on top. To me it really feels that we are (semi-)reinventing a
wheel between the lines...

> Yes, with enough force you could implement it in the gpio-74xx-mmio
> driver, but that wouldn't be mmio at all and likely completely different
> code pathes.

Got it, thanks for elaboration.

-- 
With Best Regards,
Andy Shevchenko