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Message-Id: <20220903174150.3566935-9-iskren.chernev@gmail.com>
Date: Sat, 3 Sep 2022 20:41:49 +0300
From: Iskren Chernev <iskren.chernev@...il.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rob Herring <robh+dt@...nel.org>
Cc: phone-devel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
Iskren Chernev <iskren.chernev@...il.com>,
Andy Gross <agross@...nel.org>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-kernel@...r.kernel.org
Subject: [PATCH v2 8/9] arm64: dts: qcom: sm4250: Add soc dtsi
The SM4250 is a downclocked version of the SM6115.
Signed-off-by: Iskren Chernev <iskren.chernev@...il.com>
---
arch/arm64/boot/dts/qcom/sm4250.dtsi | 38 ++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm4250.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi
new file mode 100644
index 000000000000..8cadf813e55b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, Iskren Chernev <iskren.chernev@...il.com>
+ */
+
+#include "sm6115.dtsi"
+
+&CPU0 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU1 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU2 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU3 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU4 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU5 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU6 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU7 {
+ compatible = "qcom,kryo240";
+};
--
2.37.2
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