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Message-ID: <YxS+7B0d+TqEJH3v@matsya>
Date: Sun, 4 Sep 2022 20:36:20 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Frank Wunderlich <linux@...web.de>
Cc: linux-rockchip@...ts.infradead.org,
Frank Wunderlich <frank-w@...lic-files.de>,
Kishon Vijay Abraham I <kishon@...com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Heiko Stuebner <heiko@...ech.de>,
Philipp Zabel <p.zabel@...gutronix.de>,
Yifeng Zhao <yifeng.zhao@...k-chips.com>,
Johan Jonker <jbx6244@...il.com>,
Peter Geis <pgwipeout@...il.com>,
Simon Xue <xxm@...k-chips.com>, Liang Chen <cl@...k-chips.com>,
Shawn Lin <shawn.lin@...k-chips.com>,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 3/5] phy: rockchip: Support PCIe v3
On 25-08-22, 21:38, Frank Wunderlich wrote:
> From: Shawn Lin <shawn.lin@...k-chips.com>
>
> RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566.
> It use a dedicated PCIe-phy. Add support for this.
>
> Initial support by Shawn Lin, modifications by Peter Geis and Frank
> Wunderlich.
>
> Add data-lanes property for splitting pcie-lanes across controllers.
>
> The data-lanes is an array where x=0 means lane is disabled and x > 0
> means controller x is assigned to phy lane.
Applied, thanks
--
~Vinod
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