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Message-ID: <YxTd1jBS3xk/YT6m@matsya>
Date: Sun, 4 Sep 2022 22:48:14 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Amelie Delaunay <amelie.delaunay@...s.st.com>
Cc: Jonathan Corbet <corbet@....net>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
linux-doc@...r.kernel.org, dmaengine@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Marek Vasut <marex@...x.de>
Subject: Re: [RESEND PATCH v3 0/6] STM32 DMA-MDMA chaining feature
On 29-08-22, 17:46, Amelie Delaunay wrote:
> This patchset (re)introduces STM32 DMA-MDMA chaining feature.
>
> As the DMA is not able to generate convenient burst transfer on the DDR,
> it penalises the AXI bus when accessing the DDR. While it accesses
> optimally the SRAM. The DMA-MDMA chaining then consists in having an SRAM
> buffer between DMA and MDMA, so the DMA deals with peripheral and SRAM,
> and the MDMA with SRAM and DDR.
>
> The feature relies on the fact that DMA channel Transfer Complete signal
> can trigger a MDMA channel transfer and MDMA can clear the DMA request by
> writing to DMA Interrupt Clear register.
>
> A deeper introduction can be found in patch 1.
>
> Previous implementation [1] has been dropped as nacked.
> Unlike this previous implementation (where all the stuff was embedded in
> stm32-dma driver), the user (in peripheral drivers using dma) has now to
> configure the MDMA channel.
Applied, thanks
--
~Vinod
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