linux-kernel - Re: [v3 PATCH 1/1] gpio: exar: access MPIO registers on cascaded chips

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Message-ID: <CAMRc=McBYhKkzap28H9KxHT2Vg4w1EPsEJpfu8J3JZjTcuQ41w@mail.gmail.com>
Date:   Sun, 4 Sep 2022 22:25:43 +0200
From:   Bartosz Golaszewski <brgl@...ev.pl>
To:     Qingtao Cao <qingtao.cao.au@...il.com>
Cc:     Andy Shevchenko <andy.shevchenko@...il.com>,
        Qingtao Cao <qingtao.cao@...i.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [v3 PATCH 1/1] gpio: exar: access MPIO registers on cascaded chips

On Fri, Sep 2, 2022 at 8:15 AM Qingtao Cao <qingtao.cao.au@...il.com> wrote:
>
> When EXAR xr17v35x chips are cascaded in order to access the MPIO registers
> (part of the Device Configuration Registers) of the secondary chips, an offset
> needs to be applied based on the number of primary chip's UART channels.
>
> Signed-off-by: Qingtao Cao <qingtao.cao@...i.com>
> ---

Applied, thanks!

Bart