linux-kernel - [PATCH 01/10] arm64: dts: mt8183: Fix Mali GPU clock

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Message-Id: <20220905100416.42421-2-angelogioacchino.delregno@collabora.com>
Date:   Mon,  5 Sep 2022 12:04:07 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     matthias.bgg@...il.com
Cc:     mturquette@...libre.com, sboyd@...nel.org,
        angelogioacchino.delregno@...labora.com, wenst@...omium.org,
        miles.chen@...iatek.com, rex-bc.chen@...iatek.com,
        nfraprado@...labora.com, chun-jie.chen@...iatek.com,
        jose.exposito89@...il.com, drinkcat@...omium.org,
        weiyi.lu@...iatek.com, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org
Subject: [PATCH 01/10] arm64: dts: mt8183: Fix Mali GPU clock

From: Chen-Yu Tsai <wenst@...omium.org>

The actual clock feeding into the Mali GPU on the MT8183 is from the
clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN
block, which itself is simply a pass-through placeholder for the MFGPLL
in the APMIXEDSYS block.

Fix the hardware description with the correct clock reference.

Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU")
Signed-off-by: Chen-Yu Tsai <wenst@...omium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index a70b669c49ba..402136bfd535 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1678,7 +1678,7 @@ gpu: gpu@...40000 {
 				<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
 			interrupt-names = "job", "mmu", "gpu";
 
-			clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
+			clocks = <&mfgcfg CLK_MFG_BG3D>;
 
 			power-domains =
 				<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
-- 
2.37.2