linux-kernel - Re: [PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC support

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Message-ID: <36b2b6d9-9ab4-a4bc-6476-bd5b5d3ef77e@linaro.org>
Date:   Mon, 5 Sep 2022 12:14:21 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Serge Semin <fancer.lancer@...il.com>
Cc:     Serge Semin <Sergey.Semin@...kalelectronics.ru>,
        Michal Simek <michal.simek@...inx.com>,
        Borislav Petkov <bp@...en8.de>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Tony Luck <tony.luck@...el.com>,
        Rob Herring <robh+dt@...nel.org>,
        Manish Narani <manish.narani@...inx.com>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Michail Ivanov <Michail.Ivanov@...kalelectronics.ru>,
        Pavel Parkhomenko <Pavel.Parkhomenko@...kalelectronics.ru>,
        Punnaiah Choudary Kalluri 
        <punnaiah.choudary.kalluri@...inx.com>,
        Dinh Nguyen <dinguyen@...nel.org>,
        James Morse <james.morse@....com>,
        Robert Richter <rric@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC
 support

On 26/08/2022 11:54, Serge Semin wrote:
> On Tue, Aug 23, 2022 at 11:12:28AM +0300, Krzysztof Kozlowski wrote:
>> On 22/08/2022 22:19, Serge Semin wrote:
>>> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a
>>> with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There
>>> are individual IRQs for each ECC and DFI events.The dedicated scrubber
>>
> 
>> Missing space before "The".
> 
> Ok. Thanks.
> 
>>
>>> clock source is absent since it's fully synchronous to the core clock.
>>
> 
>> You need allOf:if-then restricting this per variant.
> 
> I really don't like the allOf-if-if-etc pattern because it gets to be
> very bulky if all the vendor-specific and generic platform
> peculiarities are placed in there. I am more keen of having a
> generic DT-schema which would be then allOf-ed by the vendor-specific
> device bindings. What do you think I'd provide such design in this
> case too?

Sure, it would work.

> 
> But I'll need to move the compatible property definition to the
> "select" property. Like this:
> 
> Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml:
> +[...]
> +# Please create a separate DT-schema for your DW uMCTL2 DDR controller
> +# and make sure it's assigned with the vendor-specific compatible string.
> +select:
> +  properties:
> +    compatible:
> +      oneOf:
> +        - deprecated: true
> +          description: Synopsys DW uMCTL2 DDR controller v3.80a
> +          const: snps,ddrc-3.80a
> +        - description: Synopsys DW uMCTL2 DDR controller
> +          const: snps,dw-umctl2-ddrc
> +        - description: Xilinx ZynqMP DDR controller v2.40a
> +          const: xlnx,zynqmp-ddrc-2.40a
> +  required:
> +    - compatible

Not entirely. If you need select, then add it with compatibles, but all
descriptions and deprecated are staying in properties.


> +
> +properties:
> +  compatible: true
> +[...]
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +
> +additionalProperties: true
> 
> After that the "snps,dw-umctl2-ddrc.yaml" schema can be referenced in the
> allOf composition. Like this:
> 
> Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml:
> +[...]
> +allOf:
> +  - $ref: /schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
> +[...]
> 
> At the same time the generic DT-schema will be used to evaluate the
> "snps,ddrc-3.80a", "snps,dw-umctl2-ddrc" and "xlnx,zynqmp-ddrc-2.40a"
> device nodes as before. What do you think about that?
> 
> One big positive side of this that even though the generic schema
> can't define the IRQ/resets/clocks phandlers order because various
> platforms may have different external signals setup, the
> vendor-specific schema can and should. So I'll be able to describe the
> Baikal-T1 DDRC specific properties (clocks, clock-names, interrupts,
> interrupt-names, etc) in much more details including the reference
> signals order what you asked in the previous patch review.

It's ok. You need then second schema for your device, because something
must end with additional/unevaluatedProperties false.

Best regards,
Krzysztof