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Message-ID: <CAJF2gTRB6Rq=MbFDuoEeU4-0B1N-JVjuxrHFK6YDg59ya2R9GQ@mail.gmail.com>
Date:   Tue, 6 Sep 2022 09:33:45 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Heiko Stuebner <heiko@...ech.de>
Cc:     paul.walmsley@...ive.com, palmer@...belt.com,
        aou@...s.berkeley.edu, apatel@...tanamicro.com,
        atishp@...osinc.com, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org,
        Conor Dooley <conor.dooley@...rochip.com>,
        Andrew Jones <ajones@...tanamicro.com>
Subject: Re: [PATCH v2 5/5] riscv: check for kernel config option in t-head
 memory types errata

Reviewed-by: Guo Ren <guoren@...nel.org>

On Mon, Sep 5, 2022 at 7:10 PM Heiko Stuebner <heiko@...ech.de> wrote:
>
> The t-head variant of page-based memory types should also check first
> for the enabled kernel config option.
>
> Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head")
> Signed-off-by: Heiko Stuebner <heiko@...ech.de>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
> ---
>  arch/riscv/errata/thead/errata.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index a6f4bd8ccf3f..902e12452821 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -17,6 +17,9 @@
>  static bool errata_probe_pbmt(unsigned int stage,
>                               unsigned long arch_id, unsigned long impid)
>  {
> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> +               return false;
> +
>         if (arch_id != 0 || impid != 0)
>                 return false;
>
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

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