linux-kernel - Re: [PATCH v1 03/17] pinctrl: cy8c95x0: Allow most of the registers to be cached

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Message-ID: <CAHp75VcP6yMKQJ87Fq5ZYDGMF_39pg_qcKCa4EOz0PQEZ4A0rQ@mail.gmail.com>
Date:   Tue, 6 Sep 2022 13:25:56 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Patrick Rudolph <patrick.rudolph@...ements.com>
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 03/17] pinctrl: cy8c95x0: Allow most of the registers
 to be cached

On Tue, Sep 6, 2022 at 11:36 AM Patrick Rudolph
<patrick.rudolph@...ements.com> wrote:
>
> Hi,
> I've tested the patch series on my OpenBMC platform and it works fine.

Thank you!
I guess we may consider this as an equivalent to the formal Tested-by tag?

> I don't think it's worth the effort to implement virtual registers for
> the muxed pin configuration,
> but I won't stop you.

It's not a high priority to me anyway, but it is a good feature to
have since regmap allows us to dump registers. Moreover the listing
files in debugfs currently take a lot of time, that's how I come up
with this.

> On Mon, Sep 5, 2022 at 3:37 PM Andy Shevchenko
> <andy.shevchenko@...il.com> wrote:
> >
> > On Mon, Sep 5, 2022 at 4:34 PM Linus Walleij <linus.walleij@...aro.org> wrote:
> > > On Mon, Sep 5, 2022 at 2:57 PM Andy Shevchenko
> > > <andriy.shevchenko@...ux.intel.com> wrote:
> > > > On Fri, Sep 02, 2022 at 09:42:00PM +0300, Andy Shevchenko wrote:
> > > > > On Fri, Sep 2, 2022 at 9:36 PM Andy Shevchenko
> > > > > <andriy.shevchenko@...ux.intel.com> wrote:
> > > > > >
> > > > > > It's unclear why many of static registers were marked as volatile.
> > > > >
> > > > > the static (yeah, forgot it)
> > > > >
> > > > > > They are pretty much bidirectional and static in a sense that
> > > > > > written value is kept there until a new write or chip reset.
> > > > > > Drop those registers from the list to allow them to be cached.
> > > > >
> > > > > This patch is not correct due to indexing access. It's sneaked since I
> > > > > forgot I added it into my main repo. The proper approach should be to
> > > > > create virtual registers and decode them before use. This allows to
> > > > > cache all ports and as a benefit to debug print all port actual
> > > > > statuses.
> > > >
> > > > To be clear: With this one removed from the bunch the rest can be applied w.o.
> > > > any change.
> > >
> > > I'll give Patrick a day or two to test/review and then I'll just apply
> > > them all except this one, they are all pretty self-evident
> >
> > Sure!
> >
> > > except ACPI
> > > things which have obviously been tested on hardware
> >
> > Yes, I have a Galileo Gen 1 board which has been used for testing.
> >
> > >  so from my
> > > point of view it's good to merge.
> >
> > Thanks!


-- 
With Best Regards,
Andy Shevchenko