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Message-ID: <20220907230442.10633-1-miles.chen@mediatek.com>
Date: Thu, 8 Sep 2022 07:04:42 +0800
From: Miles Chen <miles.chen@...iatek.com>
To: <angelogioacchino.delregno@...labora.com>
CC: <chun-jie.chen@...iatek.com>, <devicetree@...r.kernel.org>,
<drinkcat@...omium.org>, <jose.exposito89@...il.com>,
<krzysztof.kozlowski+dt@...aro.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <matthias.bgg@...il.com>,
<miles.chen@...iatek.com>, <mturquette@...libre.com>,
<nfraprado@...labora.com>, <rex-bc.chen@...iatek.com>,
<robh+dt@...nel.org>, <sboyd@...nel.org>, <weiyi.lu@...iatek.com>,
<wenst@...omium.org>
Subject: Re: [PATCH 04/10] clk: mediatek: mt8183: Add clk mux notifier for MFG mux
> When the MFG PLL clock, which is upstream of the MFG clock, is changed,
> the downstream clock and consumers need to be switched away from the PLL
> over to a stable clock to avoid glitches.
>
> This is done through the use of the newly added clk mux notifier. The
> notifier is set on the mux itself instead of the upstream PLL, but in
> practice this works, as the rate change notifitcations are propogated
> throughout the sub-tree hanging off the PLL. Just before rate changes,
> the MFG mux is temporarily and transparently switched to the 26 MHz
> main crystal. After the rate change, the mux is switched back.
>
> Signed-off-by: Chen-Yu Tsai <wenst@...omium.org>
> [Angelo: Rebased to assign clk_ops in mtk_mux_nb]
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: Miles Chen <miles.chen@...iatek.com>
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