From 51bac2c734e0f2fd7e2acb406afd8a201ddf3400 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 6 Sep 2022 18:00:47 +0200 Subject: [PATCH] x86/cpu: Avoid writing MSR_IA32_TSX_CTRL when !tsx_ctrl_is_supported() On an Intel Atom N2600 (and presumable other Cedar Trail models) MSR_IA32_TSX_CTRL can be read, causing saved_msr.valid to be set for it by msr_build_context(). This causes restore_processor_state() to try and restore it, but writing this MSR is not allowed on the Intel Atom N2600 leading to: [ 99.955141] unchecked MSR access error: WRMSR to 0x122 (tried to write 0x0000000000000002) at rIP: 0xffffffff8b07a574 (native_write_msr+0x4/0x20) [ 99.955176] Call Trace: [ 99.955186] [ 99.955195] restore_processor_state+0x275/0x2c0 [ 99.955246] x86_acpi_suspend_lowlevel+0x10e/0x140 [ 99.955273] acpi_suspend_enter+0xd3/0x100 [ 99.955297] suspend_devices_and_enter+0x7e2/0x830 [ 99.955341] pm_suspend.cold+0x2d2/0x35e [ 99.955368] state_store+0x68/0xd0 [ 99.955402] kernfs_fop_write_iter+0x15e/0x210 [ 99.955442] vfs_write+0x225/0x4b0 [ 99.955523] ksys_write+0x59/0xd0 [ 99.955557] do_syscall_64+0x58/0x80 [ 99.955579] ? do_syscall_64+0x67/0x80 [ 99.955600] ? up_read+0x17/0x20 [ 99.955631] ? lock_is_held_type+0xe3/0x140 [ 99.955670] ? asm_exc_page_fault+0x22/0x30 [ 99.955688] ? lockdep_hardirqs_on+0x7d/0x100 [ 99.955710] entry_SYSCALL_64_after_hwframe+0x63/0xcd [ 99.955723] RIP: 0033:0x7f7d0fb018f7 [ 99.955741] Code: 0f 00 f7 d8 64 89 02 48 c7 c0 ff ff ff ff eb b7 0f 1f 00 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 51 c3 48 83 ec 28 48 89 54 24 18 48 89 74 24 [ 99.955753] RSP: 002b:00007ffd03292ee8 EFLAGS: 00000246 ORIG_RAX: 0000000000000001 [ 99.955771] RAX: ffffffffffffffda RBX: 0000000000000004 RCX: 00007f7d0fb018f7 [ 99.955781] RDX: 0000000000000004 RSI: 00007ffd03292fd0 RDI: 0000000000000004 [ 99.955790] RBP: 00007ffd03292fd0 R08: 000000000000c0fe R09: 0000000000000000 [ 99.955799] R10: 00007f7d0fb85fb0 R11: 0000000000000246 R12: 0000000000000004 [ 99.955808] R13: 000055df564173e0 R14: 0000000000000004 R15: 00007f7d0fbf49e0 [ 99.955910] Make tsx_ctrl_is_supported() from kernel/cpu/tsx.c non static and only pass pass MSR_IA32_TSX_CTRL to msr_build_context() when that returns true. Signed-off-by: Hans de Goede --- Important note for reviewers: In its current form this patch changes the order in which MSR-s are restored, it used to be: MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL, MSR_TSX_FORCE_ABORT, MSR_IA32_MCU_OPT_CTRL, MSR_AMD64_LS_CFG, Which is now changed to: MSR_IA32_SPEC_CTRL, MSR_TSX_FORCE_ABORT, MSR_IA32_MCU_OPT_CTRL, MSR_AMD64_LS_CFG, MSR_IA32_TSX_CTRL, I am not sure if this may have an impact on the various CPU vulnerability mitigations, please review carefully. --- arch/x86/include/asm/cpu.h | 6 ++++++ arch/x86/kernel/cpu/tsx.c | 2 +- arch/x86/power/cpu.c | 4 +++- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 8cbf623f0ecf..9047701d1966 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -49,6 +49,7 @@ extern bool handle_user_split_lock(struct pt_regs *regs, long error_code); extern bool handle_guest_split_lock(unsigned long ip); extern void handle_bus_lock(struct pt_regs *regs); u8 get_this_hybrid_cpu_type(void); +bool tsx_ctrl_is_supported(void); #else static inline void __init sld_setup(struct cpuinfo_x86 *c) {} static inline bool handle_user_split_lock(struct pt_regs *regs, long error_code) @@ -67,6 +68,11 @@ static inline u8 get_this_hybrid_cpu_type(void) { return 0; } + +static inline bool tsx_ctrl_is_supported(void) +{ + return false; +} #endif #ifdef CONFIG_IA32_FEAT_CTL void init_ia32_feat_ctl(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c index ec7bbac3a9f2..be7e8d4cc0fc 100644 --- a/arch/x86/kernel/cpu/tsx.c +++ b/arch/x86/kernel/cpu/tsx.c @@ -58,7 +58,7 @@ static void tsx_enable(void) wrmsrl(MSR_IA32_TSX_CTRL, tsx); } -static bool tsx_ctrl_is_supported(void) +bool tsx_ctrl_is_supported(void) { u64 ia32_cap = x86_read_arch_cap_msr(); diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index bb176c72891c..9c95099d1add 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -515,13 +515,15 @@ static void pm_save_spec_msr(void) { u32 spec_msr_id[] = { MSR_IA32_SPEC_CTRL, - MSR_IA32_TSX_CTRL, MSR_TSX_FORCE_ABORT, MSR_IA32_MCU_OPT_CTRL, MSR_AMD64_LS_CFG, }; + u32 tsx_ctrl_msr_id[] = { MSR_IA32_TSX_CTRL }; msr_build_context(spec_msr_id, ARRAY_SIZE(spec_msr_id)); + if (tsx_ctrl_is_supported()) + msr_build_context(tsx_ctrl_msr_id, ARRAY_SIZE(tsx_ctrl_msr_id)); } static int pm_check_save_msr(void) -- 2.37.2