lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 7 Sep 2022 12:24:45 +0300 (EEST)
From:   Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To:     Sergiu Moga <sergiu.moga@...rochip.com>
cc:     lee@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, nicolas.ferre@...rochip.com,
        alexandre.belloni@...tlin.com, claudiu.beznea@...rochip.com,
        richard.genoud@...il.com, radu_nicolae.pirea@....ro,
        gregkh@...uxfoundation.org, broonie@...nel.org,
        mturquette@...libre.com, sboyd@...nel.org, jirislaby@...nel.org,
        admin@...iphile.com, kavyasree.kotagiri@...rochip.com,
        tudor.ambarus@...rochip.com, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-spi@...r.kernel.org, linux-serial@...r.kernel.org,
        linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 09/13] tty: serial: atmel: Define BRSRCCK bitmask of
 UART IP's Mode Register

On Tue, 6 Sep 2022, Sergiu Moga wrote:

> Add definitions for the Baud Rate Source Clock bitmask of the
> Mode Register of UART IP's and its bitfields.
> 
> Signed-off-by: Sergiu Moga <sergiu.moga@...rochip.com>
> ---
> 
> 
> 
> v1 -> v2:
> - Nothing, this patch was not here before
> 
> 
> 
>  drivers/tty/serial/atmel_serial.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h
> index 70d0611e56fd..ed64035ba6c3 100644
> --- a/drivers/tty/serial/atmel_serial.h
> +++ b/drivers/tty/serial/atmel_serial.h
> @@ -68,6 +68,9 @@
>  #define		ATMEL_US_NBSTOP_1		(0 << 12)
>  #define		ATMEL_US_NBSTOP_1_5		(1 << 12)
>  #define		ATMEL_US_NBSTOP_2		(2 << 12)
> +#define	ATMEL_UA_BRSRCCK	GENMASK(13, 12)	/* Clock Selection for UART */
> +#define		ATMEL_UA_BRSRCCK_PERIPH_CLK	(0 << 12)
> +#define		ATMEL_UA_BRSRCCK_GCLK		(1 << 12)

FIELD_PREP(ATMEL_UA_BRSRCCK, ...)

>  #define	ATMEL_US_CHMODE		GENMASK(15, 14)	/* Channel Mode */
>  #define		ATMEL_US_CHMODE_NORMAL		(0 << 14)
>  #define		ATMEL_US_CHMODE_ECHO		(1 << 14)
> 

-- 
 i.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ