linux-kernel - Re: [PATCH v3 6/6] soc: sifive: ccache: define the macro for the register shifts

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Message-ID: <89e804ff-b451-c56a-a256-d3917e6c34b3@microchip.com>
Date:   Thu, 8 Sep 2022 18:31:57 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <zong.li@...ive.com>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <palmer@...belt.com>,
        <paul.walmsley@...ive.com>, <aou@...s.berkeley.edu>,
        <greentime.hu@...ive.com>, <ben.dooks@...ive.com>, <bp@...en8.de>,
        <devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        <linux-edac@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 6/6] soc: sifive: ccache: define the macro for the
 register shifts

On 08/09/2022 15:44, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Define the macro for the register shifts, it could make the code be
> more readable
> 
> Signed-off-by: Zong Li <zong.li@...ive.com>

Ahh my bad, I didn't realise you split it into another patch - sorry.

Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

> ---
>  drivers/soc/sifive/sifive_ccache.c | 16 +++++++++++-----
>  1 file changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index b3929c4d6d5b..0ddcc657c694 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -13,6 +13,7 @@
>  #include <linux/of_irq.h>
>  #include <linux/of_address.h>
>  #include <linux/device.h>
> +#include <linux/bitfield.h>
>  #include <asm/cacheinfo.h>
>  #include <soc/sifive/sifive_ccache.h>
> 
> @@ -33,6 +34,11 @@
>  #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
> 
>  #define SIFIVE_CCACHE_CONFIG 0x00
> +#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0)
> +#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8)
> +#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
> +#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
> +
>  #define SIFIVE_CCACHE_WAYENABLE 0x08
>  #define SIFIVE_CCACHE_ECCINJECTERR 0x40
> 
> @@ -87,11 +93,11 @@ static void ccache_config_read(void)
>         u32 cfg;
> 
>         cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> -
> -       pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> -               (cfg & 0xff), (cfg >> 8) & 0xff,
> -               BIT_ULL((cfg >> 16) & 0xff),
> -               BIT_ULL((cfg >> 24) & 0xff));
> +       pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n",
> +               FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg),
> +               FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg),
> +               BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)),
> +               BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg)));
> 
>         cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
>         pr_info("Index of the largest way enabled: %u\n", cfg);
> --
> 2.17.1
>