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Message-ID: <6319891ba810b_58016294a1@dwillia2-xfh.jf.intel.com.notmuch>
Date: Wed, 7 Sep 2022 23:18:03 -0700
From: Dan Williams <dan.j.williams@...el.com>
To: Robert Richter <rrichter@....com>,
Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
"Ira Weiny" <ira.weiny@...el.com>,
Ben Widawsky <bwidawsk@...nel.org>,
"Dan Williams" <dan.j.williams@...el.com>
CC: <linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Len Brown <lenb@...nel.org>, Robert Richter <rrichter@....com>
Subject: RE: [PATCH 08/15] cxl/acpi: Check RCH's CXL DVSEC capabilities
Robert Richter wrote:
> An RCH has an RCiEP connected to it with CXL DVSEC capabilities
> present and the CXL PCIe DVSEC included. Check this.
>
> Signed-off-by: Robert Richter <rrichter@....com>
> ---
> drivers/cxl/acpi.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index ffdf439adb87..f9cdf23a91a8 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -322,6 +322,8 @@ struct pci_host_bridge *cxl_find_next_rch(struct pci_host_bridge *host)
> {
> struct pci_bus *bus = host ? host->bus : NULL;
> struct acpi_device *adev;
> + struct pci_dev *pdev;
> + bool is_restricted_host;
>
> while ((bus = pci_find_next_bus(bus)) != NULL) {
> host = bus ? to_pci_host_bridge(bus->bridge) : NULL;
> @@ -343,6 +345,20 @@ struct pci_host_bridge *cxl_find_next_rch(struct pci_host_bridge *host)
> dev_dbg(&host->dev, "PCI ACPI host found: %s\n",
> acpi_dev_name(adev));
>
> + /* Check CXL DVSEC of dev 0 func 0 */
> + pdev = pci_get_slot(bus, PCI_DEVFN(0, 0));
> + is_restricted_host = pdev
> + && (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
> + && pci_find_dvsec_capability(pdev,
> + PCI_DVSEC_VENDOR_ID_CXL,
> + CXL_DVSEC_PCIE_DEVICE);
The check looks good, just the matter of integrating it into the
existing ACPI0016 device detection.
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