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Message-ID: <9609ade9-da03-6c3e-4d1a-80e97ac3b692@quicinc.com>
Date: Thu, 8 Sep 2022 12:08:23 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
<helgaas@...nel.org>
CC: <linux-pci@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <mka@...omium.org>,
<quic_vbadigan@...cinc.com>, <quic_hemantk@...cinc.com>,
<quic_nitegupt@...cinc.com>, <quic_skananth@...cinc.com>,
<quic_ramkri@...cinc.com>, <manivannan.sadhasivam@...aro.org>,
<swboyd@...omium.org>, <dmitry.baryshkov@...aro.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
"Rob Herring" <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>
Subject: Re: [PATCH v3 3/3] arm64: dts: qcom: sc7280: Add missing aggre0,
aggre1 clocks
On 9/7/2022 5:52 PM, Krzysztof Kozlowski wrote:
> On 03/09/2022 04:13, Krishna chaitanya chundru wrote:
>> Add missing aggre0, aggre1 clocks.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index e66fc67..a5ce095 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -2043,6 +2043,8 @@
>> <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
>> <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
>> <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
>> + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
>> + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
>> <&gcc GCC_DDRSS_PCIE_SF_CLK>;
>>
>> clock-names = "pipe",
>> @@ -2055,6 +2057,8 @@
>> "bus_slave",
>> "slave_q2a",
>> "tbu",
>> + "aggre0",
>> + "aggre1",
>> "ddrss_sf_tbu";
>>
> Same as binding - adding entries in the middle causes ABI issues.
>
> Best regards,
> Krzysztof
Ok I will change the order as suggested.
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