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Message-ID: <20220908012031.3354-5-mranostay@ti.com>
Date: Wed, 7 Sep 2022 18:20:30 -0700
From: Matt Ranostay <mranostay@...com>
To: <vigneshr@...com>, <nm@...com>
CC: <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, Matt Ranostay <mranostay@...com>
Subject: [PATCH v2 5/6] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
From: Aswath Govindraju <a-govindraju@...com>
The board uses lane 1 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that upto 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.
Cc: Vignesh Raghavendra <vigneshr@...com>
Cc: Nishanth Menon <nm@...com>
Acked-by: Matt Ranostay <mranostay@...com>
Signed-off-by: Aswath Govindraju <a-govindraju@...com>
---
.../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 791f235bd95f..aa75dc541842 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -147,6 +147,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
};
&wkup_pmx0 {
@@ -372,6 +378,22 @@ serdes0_pcie_link: phy@0 {
};
};
+&usb_serdes_mux {
+ idle-states = <1>; /* USB0 to SERDES lane 1 */
+};
+
+&usbss0 {
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+ ti,usb2-only;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+};
+
&mcu_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
--
2.30.2
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