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Date:   Fri, 9 Sep 2022 13:42:09 -0700
From:   Anjelique Melendez <quic_amelende@...cinc.com>
To:     <corbet@....net>, <sre@...nel.org>, <robh+dt@...nel.org>,
        <agross@...nel.org>, <andersson@...nel.org>
CC:     <krzysztof.kozlowski+dt@...aro.org>, <vkoul@...nel.org>,
        <linux-doc@...r.kernel.org>, <linux-pm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <quic_collinsd@...cinc.com>,
        "Anjelique Melendez" <quic_amelende@...cinc.com>
Subject: [RESEND PATCH v5 1/2] dt-bindings: power: reset: qcom-pon: Add new compatible "qcom,pmk8350-pon"

From: David Collins <quic_collinsd@...cinc.com>

Add a new compatible string "qcom,pmk8350-pon" for GEN3 PMIC PON
peripherals and update "reg" property.
Also, Add an optional "reg-names" property to differentiate between
GEN1/GEN2 and GEN3 peripherals. GEN1/GEN2 peripherals only need one
register address to be specified (e.g. "pon") whereas GEN3 peripherals
can have two register addresses specified ("hlos", "pbs").

Signed-off-by: David Collins <quic_collinsd@...cinc.com>
Signed-off-by: Anjelique Melendez <quic_amelende@...cinc.com>
---
 Documentation/devicetree/bindings/power/reset/qcom,pon.yaml | 50 +++++++++++++++++++++++++++---
 1 file changed, 46 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
index 353f155d..d7b6b875 100644
--- a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
+++ b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
@@ -15,18 +15,27 @@ description: |
 
   This DT node has pwrkey and resin as sub nodes.
 
-allOf:
-  - $ref: reboot-mode.yaml#
-
 properties:
   compatible:
     enum:
       - qcom,pm8916-pon
       - qcom,pms405-pon
       - qcom,pm8998-pon
+      - qcom,pmk8350-pon
 
   reg:
-    maxItems: 1
+    description: |
+      Specifies the SPMI base address for the PON (power-on) peripheral.  For
+      PMICs that have the PON peripheral (GEN3) split into PON_HLOS and PON_PBS
+      (e.g. PMK8350), this can hold addresses of both PON_HLOS and PON_PBS
+      peripherals.  In that case, the PON_PBS address needs to be specified to
+      facilitate software debouncing on some PMIC.
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    minItems: 1
+    maxItems: 2
 
   pwrkey:
     type: object
@@ -42,6 +51,39 @@ required:
 
 unevaluatedProperties: false
 
+allOf:
+  - $ref: reboot-mode.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,pm8916-pon
+              - qcom,pms405-pon
+              - qcom,pm8998-pon
+    then:
+      properties:
+        reg:
+          maxItems: 1
+        reg-names:
+          items:
+            - const: pon
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,pmk8350-pon
+    then:
+      properties:
+        reg:
+          minItems: 1
+          maxItems: 2
+        reg-names:
+          minItems: 1
+          items:
+            - const: hlos
+            - const: pbs
+
 examples:
   - |
    #include <dt-bindings/interrupt-controller/irq.h>
-- 
2.35.1

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