linux-kernel - Re: [PATCH 02/16] phy: qcom-qmp-combo: drop unused defines

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Date:   Fri, 9 Sep 2022 12:21:12 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Johan Hovold <johan+linaro@...nel.org>,
        Vinod Koul <vkoul@...nel.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...ainline.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 02/16] phy: qcom-qmp-combo: drop unused defines

On 07/09/2022 14:07, Johan Hovold wrote:
> Drop defines and enums that are unused since the QMP driver split.
> 
> Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
> ---
>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 15 ---------------
>   1 file changed, 15 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index 9ce2ab56be4c..838f7e328b55 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> @@ -28,16 +28,11 @@
>   #define SW_RESET				BIT(0)
>   /* QPHY_POWER_DOWN_CONTROL */
>   #define SW_PWRDN				BIT(0)
> -#define REFCLK_DRV_DSBL				BIT(1)
>   /* QPHY_START_CONTROL bits */
>   #define SERDES_START				BIT(0)
>   #define PCS_START				BIT(1)
> -#define PLL_READY_GATE_EN			BIT(3)
>   /* QPHY_PCS_STATUS bit */
>   #define PHYSTATUS				BIT(6)
> -#define PHYSTATUS_4_20				BIT(7)
> -/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
> -#define PCS_READY				BIT(0)

I think these defines, describing registers and bits, can go to the 
common header instead.

For the rest of the patch:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>

>   
>   /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
>   /* DP PHY soft reset */
> @@ -71,8 +66,6 @@
>   #define POWER_DOWN_DELAY_US_MIN			10
>   #define POWER_DOWN_DELAY_US_MAX			11
>   
> -#define MAX_PROP_NAME				32
> -
>   /* Define the assumed distance between lanes for underspecified device trees. */
>   #define QMP_PHY_LEGACY_LANE_STRIDE		0x400
>   
> @@ -115,22 +108,14 @@ struct qmp_phy_init_tbl {
>   
>   /* set of registers with offsets different per-PHY */
>   enum qphy_reg_layout {
> -	/* Common block control registers */
> -	QPHY_COM_SW_RESET,
> -	QPHY_COM_POWER_DOWN_CONTROL,
> -	QPHY_COM_START_CONTROL,
> -	QPHY_COM_PCS_READY_STATUS,
>   	/* PCS registers */
>   	QPHY_SW_RESET,
>   	QPHY_START_CTRL,
> -	QPHY_PCS_READY_STATUS,
>   	QPHY_PCS_STATUS,
>   	QPHY_PCS_AUTONOMOUS_MODE_CTRL,
>   	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
>   	QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
>   	QPHY_PCS_POWER_DOWN_CONTROL,
> -	/* PCS_MISC registers */
> -	QPHY_PCS_MISC_TYPEC_CTRL,
>   	/* Keep last to ensure regs_layout arrays are properly initialized */
>   	QPHY_LAYOUT_SIZE
>   };

-- 
With best wishes
Dmitry