linux-kernel - Re: [PATCH] docs/mm: Improve grammar on mmu

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Message-ID: <202209110707.9LeSzHj6-lkp@intel.com>
Date:   Sun, 11 Sep 2022 07:50:24 +0800
From:   kernel test robot <lkp@...el.com>
To:     alexlzhu@...com, linux-doc@...r.kernel.org,
        linux-kernel@...r.kernel.org, Kernel-team@...com
Cc:     kbuild-all@...ts.01.org, Alexander Zhu <alexlzhu@...com>
Subject: Re: [PATCH] docs/mm: Improve grammar on mmu_notifier documentation

Hi,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on lwn/docs-next]
[also build test WARNING on lwn-2.6/docs-next linus/master v6.0-rc4 next-20220909]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/alexlzhu-fb-com/docs-mm-Improve-grammar-on-mmu_notifier-documentation/20220908-082109
base:   git://git.lwn.net/linux.git docs-next
reproduce:
        # https://github.com/intel-lab-lkp/linux/commit/8d304367a02999d5fc990a6845ffb2c2cdf4f058
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review alexlzhu-fb-com/docs-mm-Improve-grammar-on-mmu_notifier-documentation/20220908-082109
        git checkout 8d304367a02999d5fc990a6845ffb2c2cdf4f058
        make menuconfig
        # enable CONFIG_COMPILE_TEST, CONFIG_WARN_MISSING_DOCUMENTS, CONFIG_WARN_ABI_ERRORS
        make htmldocs

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@...el.com>

All warnings (new ones prefixed by >>):

>> Documentation/mm/mmu_notifier.rst:90: WARNING: Literal block ends without a blank line; unexpected unindent.

vim +90 Documentation/mm/mmu_notifier.rst

    40	
    41	 [Time N] --------------------------------------------------------------------
    42	 CPU-thread-0  {try to write to addrA}
    43	 CPU-thread-1  {try to write to addrB}
    44	 CPU-thread-2  {}
    45	 CPU-thread-3  {}
    46	 DEV-thread-0  {read addrA and populate device TLB}
    47	 DEV-thread-2  {read addrB and populate device TLB}
    48	 [Time N+1] ------------------------------------------------------------------
    49	 CPU-thread-0  {COW_step0: {mmu_notifier_invalidate_range_start(addrA)}}
    50	 CPU-thread-1  {COW_step0: {mmu_notifier_invalidate_range_start(addrB)}}
    51	 CPU-thread-2  {}
    52	 CPU-thread-3  {}
    53	 DEV-thread-0  {}
    54	 DEV-thread-2  {}
    55	 [Time N+2] ------------------------------------------------------------------
    56	 CPU-thread-0  {COW_step1: {update page table to point to new page for addrA}}
    57	 CPU-thread-1  {COW_step1: {update page table to point to new page for addrB}}
    58	 CPU-thread-2  {}
    59	 CPU-thread-3  {}
    60	 DEV-thread-0  {}
    61	 DEV-thread-2  {}
    62	 [Time N+3] ------------------------------------------------------------------
    63	 CPU-thread-0  {preempted}
    64	 CPU-thread-1  {preempted}
    65	 CPU-thread-2  {write to addrA which is a write to new page}
    66	 CPU-thread-3  {}
    67	 DEV-thread-0  {}
    68	 DEV-thread-2  {}
    69	 [Time N+3] ------------------------------------------------------------------
    70	 CPU-thread-0  {preempted}
    71	 CPU-thread-1  {preempted}
    72	 CPU-thread-2  {}
    73	 CPU-thread-3  {write to addrB which is a write to new page}
    74	 DEV-thread-0  {}
    75	 DEV-thread-2  {}
    76	 [Time N+4] ------------------------------------------------------------------
    77	 CPU-thread-0  {preempted}
    78	 CPU-thread-1  {COW_step3: {mmu_notifier_invalidate_range_end(addrB)}}
    79	 CPU-thread-2  {}
    80	 CPU-thread-3  {}
    81	 DEV-thread-0  {}
    82	 DEV-thread-2  {}
    83	 [Time N+5] ------------------------------------------------------------------
    84	 CPU-thread-0  {preempted}
    85	 CPU-thread-1  {}
    86	 CPU-thread-2  {}
    87	 CPU-thread-3  {}
    88	 DEV-thread-0  {read addrA from old page}
    89	 DEV-thread-2  {read addrB from new page}
  > 90	Here because at time N+2 the clear page table entry was not paired with a
    91	notification to invalidate the secondary TLB, the device sees the new value for
    92	addrB before seeing the new value for addrA. This breaks total memory ordering
    93	for the device.
    94	

-- 
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