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Message-ID: <dd823b9c-fe7f-7c47-520c-bad5a798efc2@gmail.com>
Date:   Mon, 12 Sep 2022 01:33:37 -0500
From:   Frank Rowand <frowand.list@...il.com>
To:     Rob Herring <robh@...nel.org>, Lizhi Hou <lizhi.hou@....com>
Cc:     linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, helgaas@...nel.org,
        clement.leger@...tlin.com, max.zhen@....com, sonal.santan@....com,
        larry.liu@....com, brian.xu@....com, stefano.stabellini@...inx.com,
        trix@...hat.com
Subject: Re: [PATCH RFC 2/2] pci: create device tree node for selected devices

On 9/2/22 13:54, Rob Herring wrote:
> On Mon, Aug 29, 2022 at 02:43:37PM -0700, Lizhi Hou wrote:
>> The PCI endpoint device such as Xilinx Alveo PCI card maps the register
>> spaces from multiple hardware peripherals to its PCI BAR. Normally,
>> the PCI core discovers devices and BARs using the PCI enumeration process.
>> And the process does not provide a way to discover the hardware peripherals
>> been mapped to PCI BARs.

< snip >

> 
> The above bits aren't really particular to PCI, so they probably 
> belong in the DT core code. Frank will probably have thoughts on what 
> this should look like.

< snip >

I will try to look through this patch series later today (Monday 9/12
USA time - I will not be in Dublin for the conferences this week.)

-Frank

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