| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Mon, 12 Sep 2022 11:36:11 -0700
From: Alex Helms <alexander.helms.jy@...esas.com>
To: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-clk@...r.kernel.org
Cc: robh+dt@...nel.org, sboyd@...nel.org, mturquette@...libre.com,
alexander.helms.jy@...esas.com, michal.simek@...inx.com,
saeed.nowshadi@....com
Subject: [PATCH v2 0/2] Renesas Versaclock7 Bindings and Clock Driver
Device tree bindings and a common clock framework device driver
for the Renesas VersaClock7 clock generator family.
---
Changelog v2:
- Index to output number varies based on which VC7 chip model is used.
Correct bank to output reference requires converting index to output number
based on chip model.
- Differentiate between multiple instance of clock nodes by using
the value of 'clock-output-names' property.
Alex Helms (2):
dt-bindings: Renesas versaclock7 device tree bindings
clk: Renesas versaclock7 ccf device driver
.../bindings/clock/renesas,versaclock7.yaml | 64 +
MAINTAINERS | 6 +
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-versaclock7.c | 1292 +++++++++++++++++
5 files changed, 1372 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml
create mode 100755 drivers/clk/clk-versaclock7.c
base-commit: f443e374ae131c168a065ea1748feac6b2e76613
--
2.30.2
Powered by blists - more mailing lists