linux-kernel - [PATCH v3 13/14] clk: at91: sama5d2: Add Generic Clocks for UART/USART

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Message-ID: <20220913142205.162399-14-sergiu.moga@microchip.com>
Date:   Tue, 13 Sep 2022 17:22:05 +0300
From:   Sergiu Moga <sergiu.moga@...rochip.com>
To:     <lee@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <nicolas.ferre@...rochip.com>,
        <alexandre.belloni@...tlin.com>, <claudiu.beznea@...rochip.com>,
        <radu_nicolae.pirea@....ro>, <richard.genoud@...il.com>,
        <gregkh@...uxfoundation.org>, <broonie@...nel.org>,
        <mturquette@...libre.com>, <sboyd@...nel.org>,
        <jirislaby@...nel.org>, <sergiu.moga@...rochip.com>,
        <admin@...iphile.com>, <kavyasree.kotagiri@...rochip.com>,
        <tudor.ambarus@...rochip.com>
CC:     <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <linux-spi@...r.kernel.org>,
        <linux-serial@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: [PATCH v3 13/14] clk: at91: sama5d2: Add Generic Clocks for UART/USART

Add the generic clocks for UART/USART in the sama5d2 driver to allow them
to be registered in the Common Clock Framework.

Signed-off-by: Sergiu Moga <sergiu.moga@...rochip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
---


v1 -> v2:
- Added R-b tag


v2 -> v3:
- Nothing


 drivers/clk/at91/sama5d2.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index cfd0f5e23b99..84156dc52bff 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -120,6 +120,16 @@ static const struct {
 	struct clk_range r;
 	int chg_pid;
 } sama5d2_gck[] = {
+	{ .n = "flx0_gclk",   .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
+	{ .n = "flx1_gclk",   .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
+	{ .n = "flx2_gclk",   .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
+	{ .n = "flx3_gclk",   .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
+	{ .n = "flx4_gclk",   .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
+	{ .n = "uart0_gclk",  .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
+	{ .n = "uart1_gclk",  .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
+	{ .n = "uart2_gclk",  .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
+	{ .n = "uart3_gclk",  .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
+	{ .n = "uart4_gclk",  .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
 	{ .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
 	{ .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
 	{ .n = "tcb0_gclk",   .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
-- 
2.34.1