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Message-ID: <51e33996-3ff8-69cd-392d-9d5d6298fe31@microchip.com>
Date:   Tue, 13 Sep 2022 07:18:22 +0000
From:   <Claudiu.Beznea@...rochip.com>
To:     <Horatiu.Vultur@...rochip.com>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
CC:     <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <Nicolas.Ferre@...rochip.com>, <michael@...le.cc>
Subject: Re: [PATCH] ARM: dts: lan966x: Fix the interrupt number for internal
 PHYs

On 12.09.2022 22:26, Horatiu Vultur wrote:
> According to the datasheet the interrupts for internal PHYs are
> 80 and 81.
> 
> Fixes: 6ad69e07def67c ("ARM: dts: lan966x: add MIIM nodes")
> Signed-off-by: Horatiu Vultur <horatiu.vultur@...rochip.com>

Applied to at91-fixes, thanks!

> ---
>  arch/arm/boot/dts/lan966x.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index bcb130a2471d..23665a042990 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -547,13 +547,13 @@ mdio1: mdio@...0413c {
>  
>  			phy0: ethernet-phy@1 {
>  				reg = <1>;
> -				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>  				status = "disabled";
>  			};
>  
>  			phy1: ethernet-phy@2 {
>  				reg = <2>;
> -				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
>  				status = "disabled";
>  			};
>  		};

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