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Message-ID: <Yx/Nc9gyAhEZ16Ai@araj-MOBL2.amr.corp.intel.com>
Date: Mon, 12 Sep 2022 17:23:16 -0700
From: Ashok Raj <ashok.raj@...el.com>
To: Dave Hansen <dave.hansen@...el.com>
CC: Jacob Pan <jacob.jun.pan@...el.com>,
Ashok Raj <ashok_raj@...ux.intel.com>,
"Kirill A. Shutemov" <kirill@...temov.name>,
"Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Andy Lutomirski <luto@...nel.org>,
"Peter Zijlstra" <peterz@...radead.org>, <x86@...nel.org>,
Kostya Serebryany <kcc@...gle.com>,
Andrey Ryabinin <ryabinin.a.a@...il.com>,
Andrey Konovalov <andreyknvl@...il.com>,
Alexander Potapenko <glider@...gle.com>,
Taras Madan <tarasmadan@...gle.com>,
Dmitry Vyukov <dvyukov@...gle.com>,
"H . J . Lu" <hjl.tools@...il.com>,
Andi Kleen <ak@...ux.intel.com>,
Rick Edgecombe <rick.p.edgecombe@...el.com>,
<linux-mm@...ck.org>, <linux-kernel@...r.kernel.org>,
Ashok Raj <ashok.raj@...el.com>
Subject: Re: [PATCHv8 00/11] Linear Address Masking enabling
On Mon, Sep 12, 2022 at 02:41:56PM -0700, Dave Hansen wrote:
> On 9/12/22 13:39, Jacob Pan wrote:
> >>> + if (pasid_valid(mm->pasid) && !forced) {
> > I don't think this works since we have lazy pasid free. for example,
> > after all the devices did sva_unbind, mm->pasid we'll remain valid until
> > mmdrop(). LAM should be supported in this case.
>
> Nah, it works fine.
>
> It just means that the rules are "you can't do LAM if your process
> *EVER* got a PASID" instead of "you can't do LAM if you are actively
> using your PASID".
>
> We knew that PASID use would be a one-way trip for a process when we
> moved to the simplified implementation. This is just more fallout from
> that. It's fine.
Agree.
>
> > Perhaps, we could introduce another prctl flag for SVA, PR_GET_SVA?
> > Both iommu driver and LAM can set/query the flag. LAM applications may not
> > be the only ones want to know if share virtual addressing is on.
>
> I don't think it's a good idea to add yet more UABI around this issue.
> Won't the IOMMU folks eventually get their hardware in line with LAM?
> Isn't this situation temporary?
This is more than just the IOMMU change, since this involves device end,
ability to report tagging feature, communicating the width to ignore
etc. I suspect PCIe changes are required for the device end which would
be a long pole.
I suspect this would be moderately permanent :-) memory tagging is more
of a niche use case, and hurting general IO devices has lots of design
touch points that makes it difficult to close in short order.
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