linux-kernel - Re: [PATCH v5 7/7] riscv: Add cache information in AUX vector

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Message-ID: <88298aa6-6786-12a7-8559-2b49ee1081e2@microchip.com>
Date:   Tue, 13 Sep 2022 10:34:44 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <zong.li@...ive.com>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <palmer@...belt.com>,
        <paul.walmsley@...ive.com>, <aou@...s.berkeley.edu>,
        <greentime.hu@...ive.com>, <ben.dooks@...ive.com>, <bp@...en8.de>,
        <devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        <linux-edac@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 7/7] riscv: Add cache information in AUX vector

On 13/09/2022 07:18, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Greentime Hu <greentime.hu@...ive.com>
> 
> There are no standard CSR registers to provide cache information, the
> way for RISC-V is to get this information from DT. sysconf syscall
> could use them to get information of cache through AUX vector.
> 
> The result of 'getconf -a|grep -i cache' as follows:
> LEVEL1_ICACHE_SIZE                 32768
> LEVEL1_ICACHE_ASSOC                2
> LEVEL1_ICACHE_LINESIZE             64
> LEVEL1_DCACHE_SIZE                 32768
> LEVEL1_DCACHE_ASSOC                4
> LEVEL1_DCACHE_LINESIZE             64
> LEVEL2_CACHE_SIZE                  524288
> LEVEL2_CACHE_ASSOC                 8
> LEVEL2_CACHE_LINESIZE              64
> LEVEL3_CACHE_SIZE                  4194304
> LEVEL3_CACHE_ASSOC                 16
> LEVEL3_CACHE_LINESIZE              64
> LEVEL4_CACHE_SIZE                  0
> LEVEL4_CACHE_ASSOC                 0
> LEVEL4_CACHE_LINESIZE              0
> 
> Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
> Signed-off-by: Zong Li <zong.li@...ive.com>
> Suggested-by: Zong Li <zong.li@...ive.com>
> ---

This _looks_ completely sane to me, but it is well beyond my
paygrade... FWIW:
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

>   arch/riscv/include/asm/elf.h         | 4 ++++
>   arch/riscv/include/uapi/asm/auxvec.h | 4 +++-
>   2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
> index 14fc7342490b..e7acffdf21d2 100644
> --- a/arch/riscv/include/asm/elf.h
> +++ b/arch/riscv/include/asm/elf.h
> @@ -99,6 +99,10 @@ do {                                                         \
>                  get_cache_size(2, CACHE_TYPE_UNIFIED));         \
>          NEW_AUX_ENT(AT_L2_CACHEGEOMETRY,                        \
>                  get_cache_geometry(2, CACHE_TYPE_UNIFIED));     \
> +       NEW_AUX_ENT(AT_L3_CACHESIZE,                            \
> +               get_cache_size(3, CACHE_TYPE_UNIFIED));         \
> +       NEW_AUX_ENT(AT_L3_CACHEGEOMETRY,                        \
> +               get_cache_geometry(3, CACHE_TYPE_UNIFIED));     \
>   } while (0)
>   #define ARCH_HAS_SETUP_ADDITIONAL_PAGES
>   struct linux_binprm;
> diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h
> index 32c73ba1d531..fb187a33ce58 100644
> --- a/arch/riscv/include/uapi/asm/auxvec.h
> +++ b/arch/riscv/include/uapi/asm/auxvec.h
> @@ -30,8 +30,10 @@
>   #define AT_L1D_CACHEGEOMETRY   43
>   #define AT_L2_CACHESIZE                44
>   #define AT_L2_CACHEGEOMETRY    45
> +#define AT_L3_CACHESIZE                46
> +#define AT_L3_CACHEGEOMETRY    47
> 
>   /* entries in ARCH_DLINFO */
> -#define AT_VECTOR_SIZE_ARCH    7
> +#define AT_VECTOR_SIZE_ARCH    9
> 
>   #endif /* _UAPI_ASM_RISCV_AUXVEC_H */
> --
> 2.17.1
>