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Message-Id: <1663075485-20591-1-git-send-email-lixiaochun.2888@163.com>
Date: Tue, 13 Sep 2022 21:24:45 +0800
From: Xiaochun Lee <lixiaochun.2888@....com>
To: nirmal.patel@...ux.intel.com, jonathan.derrick@...ux.dev
Cc: lpieralisi@...nel.org, robh@...nel.org, kw@...ux.com,
bhelgaas@...gle.com, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org, Xiaochun Lee <lixc17@...ovo.com>
Subject: [PATCH v1] PCI: Set no io resource for bridges that behind VMD controller
From: Xiaochun Lee <lixc17@...ovo.com>
When enable VMDs on Intel CPUs, VMD controllers(8086:28c0) be
recognized by VMD driver and there are many failed messages of
BAR 13 when scan the bridges and assign IO resource behind it
as listed below, the bridge wants to get 0x6000 as its IO
resource, but there is no IO resources on the host bridge.
VMD host bridge resources:
vmd 0000:64:00.5: PCI host bridge to bus 10000:80
pci_bus 10000:80: root bus resource [bus 80-9f]
pci_bus 10000:80: root bus resource [mem 0xe0000000-0xe1ffffff]
pci_bus 10000:80: root bus resource [mem 0x24ffff02010-0x24fffffffff 64bit]
Failed messages of BAR#13:
pci 10000:80:02.0: BAR 13: no space for [io size 0x1000]
pci 10000:80:02.0: BAR 13: failed to assign [io size 0x1000]
pci 10000:80:03.0: BAR 13: no space for [io size 0x1000]
pci 10000:80:03.0: BAR 13: failed to assign [io size 0x1000]
VMD-enabled root ports use
Enhanced Configuration Access Mechanism (ECAM) access
PCI Express configuration space, and offer VMD_CFGBAR as
base of PCI Express configuration space for the bridges
behind it. The configuration space includes IO resources,
but these IO resources are not actually used on X86,
especially the NVMes as device connected on this hot plug
bridges, and it can result in BAR#13 assign IO resource
failed. So we clear IO resources by setting an IO base value
greater than limit to these bridges. Hence, we can leverage
kernel parameter "pci=hpiosize=0KB" to avoid this failed
messages show out.
Signed-off-by: Xiaochun Lee <lixc17@...ovo.com>
---
drivers/pci/quirks.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 4944798..f8a37f0 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5956,3 +5956,60 @@ static void aspm_l1_acceptable_latency(struct pci_dev *dev)
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
#endif
+
+#if defined(CONFIG_X86_64) || defined(CONFIG_X86)
+/*
+ * VMD-enabled root ports use Enhanced Configuration Access Mechanism (ECAM)
+ * access PCI Express configuration space, and offer VMD_CFGBAR as
+ * base of PCI Express configuration space for the bridges behind it.
+ * The configuration space includes IO resources, but these IO
+ * resources are not actually used on X86, especially the NVMes as
+ * device connnected on this hot plug bridges, and it can result
+ * in BAR#13 assign IO resource failed. So we clear IO resources
+ * by setting an IO base value greater than limit to these bridges.
+ * Hence, append kernel parameter "pci=hpiosize=0KB" can avoid
+ * this BAR#13 failed messages show out.
+ */
+static void quirk_vmd_no_iosize(struct pci_dev *bridge)
+{
+ u8 io_base_lo, io_limit_lo;
+ u16 io_low;
+ u32 io_upper16;
+ unsigned long io_mask, base, limit;
+
+ io_mask = PCI_IO_RANGE_MASK;
+ if (bridge->io_window_1k)
+ io_mask = PCI_IO_1K_RANGE_MASK;
+
+ /* VMD Domain */
+ if (is_vmd(bridge->bus) && bridge->is_hotplug_bridge) {
+ pci_read_config_byte(bridge, PCI_IO_BASE, &io_base_lo);
+ pci_read_config_byte(bridge, PCI_IO_LIMIT, &io_limit_lo);
+ base = (io_base_lo & io_mask) << 8;
+ limit = (io_limit_lo & io_mask) << 8;
+ if (limit >= base) {
+ /* if there are defined io ports behind the bridge on x86,
+ * we clear it, since there is only 64KB IO resource on it,
+ * beyond that, hotplug io bridges don't needs IO port resource,
+ * such as NVMes attach on it. So the corresponding range must be
+ * turned off by writing base value greater than limit to the
+ * bridge's base/limit registers.
+ */
+
+ /* Clear upper 16 bits of I/O base/limit */
+ io_upper16 = 0;
+ /* set base value greater than limit */
+ io_low = 0x00f0;
+
+ /* Temporarily disable the I/O range before updating PCI_IO_BASE */
+ pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
+ /* Update lower 16 bits of I/O base/limit */
+ pci_write_config_word(bridge, PCI_IO_BASE, io_low);
+ /* Update upper 16 bits of I/O base/limit */
+ pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
+ }
+ }
+}
+DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_ANY_ID, PCI_ANY_ID,
+ PCI_CLASS_BRIDGE_PCI, 8, quirk_vmd_no_iosize);
+#endif
--
1.8.3.1
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