linux-kernel - [PATCH 5.19 105/192] riscv: dts: microchip: use an mpfs specific l2 compatible

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Date:   Tue, 13 Sep 2022 16:03:31 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Sasha Levin <sashal@...nel.org>
Subject: [PATCH 5.19 105/192] riscv: dts: microchip: use an mpfs specific l2 compatible

From: Conor Dooley <conor.dooley@...rochip.com>

[ Upstream commit 0dec364ffeb6149aae572ded1e34d4b444c23be6 ]

PolarFire SoC does not have the same l2 cache controller as the fu540,
featuring an extra interrupt. Appease the devicetree checker overlords
by adding a PolarFire SoC specific compatible to fix the below sort of
warnings:

mpfs-polarberry.dtb: cache-controller@...0000: interrupts: [[1], [3], [4], [2]] is too long

Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@...onical.com>
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 9f5bce1488d93..9bf37ef379509 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -161,7 +161,7 @@
 		ranges;
 
 		cctrllr: cache-controller@...0000 {
-			compatible = "sifive,fu540-c000-ccache", "cache";
+			compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
 			reg = <0x0 0x2010000 0x0 0x1000>;
 			cache-block-size = <64>;
 			cache-level = <2>;
-- 
2.35.1