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Message-ID: <cee07cc1-4972-df69-0451-1f345c0d16f3@oss.nxp.com>
Date:   Wed, 14 Sep 2022 08:36:08 +0800
From:   Peng Fan <peng.fan@....nxp.com>
To:     jassisinghbrar@...il.com, shawnguo@...nel.org,
        s.hauer@...gutronix.de
Cc:     kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Peng Fan <peng.fan@....com>, Liu Ying <victor.liu@....com>
Subject: Re: [PATCH] mailbox: imx: fix RST channel support

Hi Jassi,

On 8/29/2022 11:37 AM, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@....com>
> 
> Because IMX_MU_xCR_MAX was increased to 5, some mu cfgs were not updated
> to include the CR register. Add the missed CR register to xcr array.
> 
> Fixes: 3d38ac9c40bd ("mailbox: imx: fix RST channel support")
> Reported-by: Liu Ying <victor.liu@....com>
> Signed-off-by: Peng Fan <peng.fan@....com>

Would you pick up this patch for 6.0 release?

Thanks,
Peng.

> ---
> 
> V1:
>   Tested on i.MX93/8ULP/8QXP/7ULP
> 
>   drivers/mailbox/imx-mailbox.c | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
> index 02922073c9ef..20f2ec880ad6 100644
> --- a/drivers/mailbox/imx-mailbox.c
> +++ b/drivers/mailbox/imx-mailbox.c
> @@ -904,7 +904,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
>   	.xTR	= 0x20,
>   	.xRR	= 0x40,
>   	.xSR	= {0x60, 0x60, 0x60, 0x60},
> -	.xCR	= {0x64, 0x64, 0x64, 0x64},
> +	.xCR	= {0x64, 0x64, 0x64, 0x64, 0x64},
>   };
>   
>   static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
> @@ -927,7 +927,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
>   	.xTR	= 0x200,
>   	.xRR	= 0x280,
>   	.xSR	= {0xC, 0x118, 0x124, 0x12C},
> -	.xCR	= {0x110, 0x114, 0x120, 0x128},
> +	.xCR	= {0x8, 0x110, 0x114, 0x120, 0x128},
>   };
>   
>   static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
> @@ -938,7 +938,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
>   	.xTR	= 0x200,
>   	.xRR	= 0x280,
>   	.xSR	= {0xC, 0x118, 0x124, 0x12C},
> -	.xCR	= {0x110, 0x114, 0x120, 0x128},
> +	.xCR	= {0x8, 0x110, 0x114, 0x120, 0x128},
>   };
>   
>   static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
> @@ -949,7 +949,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
>   	.xTR	= 0x0,
>   	.xRR	= 0x10,
>   	.xSR	= {0x20, 0x20, 0x20, 0x20},
> -	.xCR	= {0x24, 0x24, 0x24, 0x24},
> +	.xCR	= {0x24, 0x24, 0x24, 0x24, 0x24},
>   };
>   
>   static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
> @@ -960,7 +960,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
>   	.xTR	= 0x0,
>   	.xRR	= 0x10,
>   	.xSR	= {0x20, 0x20, 0x20, 0x20},
> -	.xCR	= {0x24, 0x24, 0x24, 0x24},
> +	.xCR	= {0x24, 0x24, 0x24, 0x24, 0x24},
>   };
>   
>   static const struct of_device_id imx_mu_dt_ids[] = {

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