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Message-Id: <20220914214703.29706-5-leoyang.li@nxp.com>
Date:   Wed, 14 Sep 2022 16:46:56 -0500
From:   Li Yang <leoyang.li@....com>
To:     shawnguo@...nel.org, devicetree@...r.kernel.org
Cc:     robh+dt@...nel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, Hou Zhiqiang <Zhiqiang.Hou@....com>,
        Li Yang <leoyang.li@....com>
Subject: [PATCH v2 04/11] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes

From: Hou Zhiqiang <Zhiqiang.Hou@....com>

The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller node.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
Signed-off-by: Li Yang <leoyang.li@....com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index d04d4ac66d2a..e1c5d685a9e3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -901,6 +901,7 @@ pcie1: pcie@...0000 {
 					<0000 0 0 2 &gic 0 111 0x4>,
 					<0000 0 0 3 &gic 0 112 0x4>,
 					<0000 0 0 4 &gic 0 113 0x4>;
+			fsl,pcie-scfg = <&scfg 0>;
 			status = "disabled";
 		};
 
@@ -927,6 +928,7 @@ pcie2: pcie@...0000 {
 					<0000 0 0 2 &gic 0 121 0x4>,
 					<0000 0 0 3 &gic 0 122 0x4>,
 					<0000 0 0 4 &gic 0 123 0x4>;
+			fsl,pcie-scfg = <&scfg 1>;
 			status = "disabled";
 		};
 
@@ -953,6 +955,7 @@ pcie3: pcie@...0000 {
 					<0000 0 0 2 &gic 0 155 0x4>,
 					<0000 0 0 3 &gic 0 156 0x4>,
 					<0000 0 0 4 &gic 0 157 0x4>;
+			fsl,pcie-scfg = <&scfg 2>;
 			status = "disabled";
 		};
 
-- 
2.37.1

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