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Message-ID: <3d79125c-74c4-315e-cfd2-2263d3714716@quicinc.com>
Date: Wed, 14 Sep 2022 14:28:12 +0530
From: Sibi Sankar <quic_sibis@...cinc.com>
To: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>,
<linux-remoteproc@...r.kernel.org>, <agross@...nel.org>,
<bjorn.andersson@...aro.org>, <lgirdwood@...il.com>,
<broonie@...nel.org>, <robh+dt@...nel.org>,
<quic_plai@...cinc.com>, <bgoswami@...cinc.com>, <perex@...ex.cz>,
<tiwai@...e.com>, <srinivas.kandagatla@...aro.org>,
<quic_rohkumar@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <swboyd@...omium.org>,
<judyhsiao@...omium.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH v6 1/8] dt-bindings: remoteproc: qcom: Add SC7280 ADSP
support
Hey Srinivas,
Thanks for the patch series.
On 9/8/22 6:53 PM, Srinivasa Rao Mandadapu wrote:
> Add ADSP PIL loading support for SC7280 SoCs.
>
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
> Reviewed-by: Rob Herring <robh@...nel.org>
> ---
> Changes since V5:
> -- Remove qcom,adsp-memory-regions property.
> Changes since V4:
> -- Update halt registers description in dt bindings.
>
> .../bindings/remoteproc/qcom,sc7280-adsp-pil.yaml | 175 +++++++++++++++++++++
> 1 file changed, 175 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml
> new file mode 100644
> index 0000000..1428522
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml
> @@ -0,0 +1,175 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-adsp-pil.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SC7280 ADSP Peripheral Image Loader
> +
> +maintainers:
> + - Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
> +
> +description:
> + This document defines the binding for a component that loads and boots firmware
s/defines the binding/describes the hardware.
> + on the Qualcomm Technology Inc. ADSP.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sc7280-adsp-pil
> +
> + reg:
> + minItems: 1
> + items:
> + - description: qdsp6ss register
> + - description: efuse q6ss register
> +
> + interrupts:
> + items:
> + - description: Watchdog interrupt
> + - description: Fatal interrupt
> + - description: Ready interrupt
> + - description: Handover interrupt
> + - description: Stop acknowledge interrupt
> + - description: Shutdown acknowledge interrupt
> +
> + interrupt-names:
> + items:
> + - const: wdog
> + - const: fatal
> + - const: ready
> + - const: handover
> + - const: stop-ack
> + - const: shutdown-ack
> +
> + clocks:
> + items:
> + - description: XO clock
> + - description: GCC CFG NOC LPASS clock
> + - description: LPASS AHBS AON clock
> + - description: LPASS AHBM AON clock
> + - description: QDSP XO clock
> + - description: Q6SP6SS SLEEP clock
> + - description: Q6SP6SS CORE clock
> +
> + clock-names:
> + items:
> + - const: xo
> + - const: gcc_cfg_noc_lpass
> + - const: lpass_ahbs_aon_cbcr
> + - const: lpass_ahbm_aon_cbcr
> + - const: qdsp6ss_xo
> + - const: qdsp6ss_sleep
> + - const: qdsp6ss_core
> +
> + power-domains:
> + items:
> + - description: LCX power domain
Doesn't it need the LMX pd as well?
> +
> + resets:
> + items:
> + - description: PDC AUDIO SYNC RESET
> + - description: CC LPASS restart
> +
> + reset-names:
> + items:
> + - const: pdc_sync
> + - const: cc_lpass
> +
> + memory-region:
> + maxItems: 1
> + description: Reference to the reserved-memory for the Hexagon core
> +
> + qcom,halt-regs:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle reference to a syscon representing TCSR followed by the
> + four offsets within syscon for q6, CE, AXI and qv6 halt registers.
> + items:
> + items:
> + - description: phandle to TCSR MUTEX
> + - description: offset to q6 halt registers
> + - description: offset to CE halt registers
> + - description: offset to AXI halt registers
> + - description: offset to qv6 halt registers
> +
> + qcom,smem-states:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: States used by the AP to signal the Hexagon core
> + items:
> + - description: Stop the modem
> +
> + qcom,smem-state-names:
> + $ref: /schemas/types.yaml#/definitions/string
You can skip ref and items.
> + description: The names of the state bits used for SMP2P output
> + items:
> + - const: stop
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> + - power-domains
> + - resets
> + - reset-names
> + - qcom,halt-regs
> + - memory-region
> + - qcom,smem-states
> + - qcom,smem-state-names
You probably also need to mention qcom,qmp as a required property.
Not sure why you choose to skip glink-edge as well.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> + #include <dt-bindings/clock/qcom,lpass-sc7280.h>
> + #include <dt-bindings/reset/qcom,sdm845-aoss.h>
> + #include <dt-bindings/reset/qcom,sdm845-pdc.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + remoteproc@...0000 {
> + compatible = "qcom,sc7280-adsp-pil";
> + reg = <0x03000000 0x5000>,
> + <0x0355b000 0x10>;
> +
> + interrupts-extended = <&pdc 162 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
> +
> + interrupt-names = "wdog", "fatal", "ready",
> + "handover", "stop-ack", "shutdown-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_CFG_NOC_LPASS_CLK>,
> + <&lpasscc LPASS_Q6SS_AHBM_CLK>,
> + <&lpasscc LPASS_Q6SS_AHBS_CLK>,
> + <&lpasscc LPASS_QDSP6SS_XO_CLK>,
> + <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
> + <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
> + clock-names = "xo", "gcc_cfg_noc_lpass",
> + "lpass_ahbs_aon_cbcr",
> + "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
> + "qdsp6ss_sleep", "qdsp6ss_core";
> +
> + power-domains = <&rpmhpd SC7280_LCX>;
> +
> + resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
> + <&aoss_reset AOSS_CC_LPASS_RESTART>;
> + reset-names = "pdc_sync", "cc_lpass";
> +
> + qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
> +
> + memory-region = <&adsp_mem>;
> +
> + qcom,smem-states = <&adsp_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + };
>
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