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Date: Wed, 14 Sep 2022 15:09:05 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: <robh+dt@...nel.org>, <lee.jones@...aro.org>,
<krzysztof.kozlowski@...aro.org>,
<krzysztof.kozlowski+dt@...aro.org>, <kishon@...com>,
<vkoul@...nel.org>, <dan.carpenter@...cle.com>,
<grygorii.strashko@...com>, <rogerq@...nel.org>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-phy@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>, <sjakhade@...ence.com>,
<s-vadapalli@...com>
Subject: [PATCH 0/6] Add support for J721e CPSW9G and SGMII mode
Add compatible for J721e CPSW9G.
Add support for SGMII mode in phy-gmii-sel driver for CPSW5G of J7200 and
CPSW9G of J721e.
Add SGMII support in phy-j721e-wiz driver for J721E_WIZ_16G.
Add support for PCIe + SGMII multilink configuration in phy-cadence-sierra
driver.
Siddharth Vadapalli (5):
dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e
phy: ti: gmii-sel: Add support for configuring CPSW5G ports in SGMII
mode
phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J721e
phy: ti: gmii-sel: Enable SGMII mode configuration for J721E
phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J721E
Swapnil Jakhade (1):
phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration
.../bindings/phy/ti,phy-gmii-sel.yaml | 52 ++++++-
drivers/phy/cadence/phy-cadence-sierra.c | 141 +++++++++++++++++-
drivers/phy/ti/phy-gmii-sel.c | 57 +++++--
drivers/phy/ti/phy-j721e-wiz.c | 1 +
4 files changed, 232 insertions(+), 19 deletions(-)
--
2.25.1
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