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Message-ID: <06eb15ea-56b3-4f18-be18-3fc710cef779@collabora.com>
Date: Wed, 14 Sep 2022 15:46:41 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Johnson Wang <johnson.wang@...iatek.com>, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, sboyd@...nel.org
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Project_Global_Chrome_Upstream_Group@...iatek.com,
Edward-JW Yang <edward-jw.yang@...iatek.com>
Subject: Re: [PATCH v2 2/4] dt-bindings: arm: mediatek: Add new bindings of
MediaTek frequency hopping
Il 14/09/22 14:45, Johnson Wang ha scritto:
> Add the new binding documentation for MediaTek frequency hopping
> and spread spectrum clocking control.
>
> Co-developed-by: Edward-JW Yang <edward-jw.yang@...iatek.com>
> Signed-off-by: Edward-JW Yang <edward-jw.yang@...iatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@...iatek.com>
> ---
> .../bindings/arm/mediatek/mediatek,fhctl.yaml | 47 +++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml
> new file mode 100644
> index 000000000000..7b0fd0889bb6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml
> @@ -0,0 +1,47 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,fhctl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek frequency hopping and spread spectrum clocking control
> +
> +maintainers:
> + - Edward-JW Yang <edward-jw.yang@...iatek.com>
> +
> +description: |
> + Frequency hopping control (FHCTL) is a piece of hardware that control
> + some PLLs to adopt "hopping" mechanism to adjust their frequency.
> + Spread spectrum clocking (SSC) is another function provided by this hardware.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8186-fhctl
> +
> + reg:
> + maxItems: 1
There are still a few issues in this binding that I can immediately see...
> +
> + clocks:
MT8195 has 23 PLLs, MT8186 has 14, but perhaps in the future we may see
something more than that on some newer SoC, so...
clocks:
maxItems: 30
> + description: Phandles of the PLL with FHCTL hardware capability.
> +
> + mediatek,hopping-ssc-percents:
> + description: The percentage of spread spectrum clocking for one PLL.
> + $ref: /schemas/types.yaml#/definitions/uint32
This is an array, so...
$ref: /schemas/types.yaml#/definitions/uint32-array
...also, maxItems?
and you should also specify:
default: 0 <- because, by default, SSC is disabled
minimum: 0 <- because this is the minimum accepted value
Regards,
Angelo
> + maximum: 8
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8186-clk.h>
> + fhctl: fhctl@...0ce00 {
> + compatible = "mediatek,mt8186-fhctl";
> + reg = <0x1000c000 0xe00>;
> + clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
> + mediatek,hopping-ssc-percents = <3>;
> + };
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