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Date: Tue, 13 Sep 2022 21:25:54 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Richard Acayan <mailingradian@...il.com>
Cc: linux-arm-msm@...r.kernel.org, Andy Gross <agross@...nel.org>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht
Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: qcom: add sdm670 pinctrl
On Tue, Sep 13, 2022 at 09:44:03PM -0400, Richard Acayan wrote:
> There is a new driver for the Snapdragon 670 TLMM (Top-Level Mode
> Multiplexer). Document it.
>
> Adapted from qcom,sm6350-pinctrl.yaml in the same directory at
> commit c09acbc499e8 ("dt-bindings: pinctrl: use pinctrl.yaml").
>
> Signed-off-by: Richard Acayan <mailingradian@...il.com>
> ---
> .../bindings/pinctrl/qcom,sdm670-pinctrl.yaml | 128 ++++++++++++++++++
> 1 file changed, 128 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm670-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-pinctrl.yaml
> new file mode 100644
> index 000000000000..28a690bfd348
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-pinctrl.yaml
> @@ -0,0 +1,128 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. SDM670 TLMM block
> +
> +maintainers:
> + - Richard Acayan <mailingradian@...il.com>
> +
> +description: |
> + This binding describes the Top Level Mode Multiplexer (TLMM) block found
> + in the SDM670 platform.
> +
> +allOf:
> + - $ref: "pinctrl.yaml#"
> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,sdm670-pinctrl
> +
> + reg:
> + maxItems: 1
> +
> + interrupts: true
> + interrupt-controller: true
> + '#interrupt-cells': true
> + gpio-controller: true
> + gpio-reserved-ranges: true
> + '#gpio-cells': true
> + gpio-ranges: true
> + wakeup-parent: true
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +patternProperties:
> + '-state$':
> + oneOf:
> + - $ref: "#/$defs/qcom-sdm670-tlmm-state"
> + - patternProperties:
> + ".*":
Please see
https://lore.kernel.org/linux-arm-msm/20220912061746.6311-2-krzysztof.kozlowski@linaro.org/
> + $ref: "#/$defs/qcom-sdm670-tlmm-state"
> +
> +$defs:
> + qcom-sdm670-tlmm-state:
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
> +
> + properties:
> + pins:
> + description:
> + List of gpio pins affected by the properties specified in this
> + subnode.
> + items:
> + oneOf:
> + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[01])$"
You only have gpio0 through gpio149 in the implementation, so the last
15[01] is not applicable.
> + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
> + sdc2_cmd, sdc2_data ]
You're missing ufs_reset in this list.
> + minItems: 1
> + maxItems: 36
> +
> + function:
Please see
https://lore.kernel.org/linux-arm-msm/20220912061746.6311-6-krzysztof.kozlowski@linaro.org/
Regards,
Bjorn
> + description:
> + Specify the alternative function to be configured for the specified
> + pins.
> +
> + enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
> + atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
> + atest_usb22, atest_usb23, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
> + cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, dbg_out, ddr_bist,
> + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
> + gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update,
> + lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
> + mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
> + pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable,
> + qlink_request, qua_mi2s, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2,
> + qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sdc4_clk,
> + sdc4_cmd, sdc4_data, sd_write, sec_mi2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2,
> + tgu_ch3, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, tsif2_clk,
> + tsif2_data, tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
> + uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,
> + vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data, ]
> +
> +
> + bias-disable: true
> + bias-pull-down: true
> + bias-pull-up: true
> + drive-strength: true
> + input-enable: true
> + output-high: true
> + output-low: true
> +
> + required:
> + - pins
> + - function
> +
> + additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + pinctrl@...0000 {
> + compatible = "qcom,sdm670-pinctrl";
> + reg = <0x03400000 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 151>;
> +
> + qup-i2c9-state {
> + pinmux {
> + pins = "gpio6", "gpio7";
> + function = "qup9";
> + };
> + };
> + };
> +...
> --
> 2.37.3
>
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