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Message-Id: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Thu, 15 Sep 2022 19:15:48 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Cc: Heiko Stuebner <heiko@...ech.de>,
Atish Patra <atishp@...osinc.com>,
Conor Dooley <conor.dooley@...rochip.com>,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-renesas-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH v3 00/10] Add support for Renesas RZ/Five SoC
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Hi All,
The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
entry-class social infrastructure gateway control and industrial gateway
control.
This patch series adds initial SoC DTSi support for Renesas RZ/Five
(R9A07G043) SoC and updates the bindings for the same. Below is the list
of IP blocks added in the initial SoC DTSI which can be used to boot via
initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC
Useful links:
-------------
[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
[1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Patch series depends on:
-----------------------
[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220914134211.199631-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220915165256.352843-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
v2->v3:
-------
* Re-used RZ/G2UL SMARC EVK SoM and carrier DTSI
* Included RB tags
* Rebased patches on -next
v2: https://lore.kernel.org/all/20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
v1: https://lore.kernel.org/lkml/20220726180623.1668-5-prabhakar.mahadev-lad.rj@bp.renesas.com/
Below are the logs from RZ/Five SMARC EVK:
------------------------------------------
/ # uname -ra
Linux (none) 6.0.0-rc5-next-20220915-00016-g0f0153102a13 #121 SMP Thu Sep 15 16:54:44 BST 2022 riscv64 GNU/Linux
/ # cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv64imafdc
mmu : sv39
uarch : andestech,ax45mp
mvendorid : 0x31e
marchid : 0x8000000000008a45
mimpid : 0x500
/ # cat /proc/interrupts
CPU0
1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
2: 0 SiFive PLIC 414 Level 1004b800.serial:rx full
3: 178 SiFive PLIC 415 Level 1004b800.serial:tx empty
4: 0 SiFive PLIC 413 Level 1004b800.serial:break
5: 1879569 RISC-V INTC 5 Edge riscv-timer
6: 37 SiFive PLIC 416 Level 1004b800.serial:rx ready
IPI0: 0 Rescheduling interrupts
IPI1: 0 Function call interrupts
IPI2: 0 CPU stop interrupts
IPI3: 0 IRQ work interrupts
IPI4: 0 Timer broadcast interrupts
/ # cat /proc/meminfo
MemTotal: 882356 kB
MemFree: 861740 kB
MemAvailable: 859488 kB
Buffers: 0 kB
Cached: 1796 kB
SwapCached: 0 kB
Active: 0 kB
Inactive: 80 kB
Active(anon): 0 kB
Inactive(anon): 80 kB
Active(file): 0 kB
Inactive(file): 0 kB
Unevictable: 1796 kB
Mlocked: 0 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 0 kB
Writeback: 0 kB
AnonPages: 116 kB
Mapped: 1136 kB
Shmem: 0 kB
KReclaimable: 6732 kB
Slab: 11932 kB
SReclaimable: 6732 kB
SUnreclaim: 5200 kB
KernelStack: 540 kB
PageTables: 32 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 441176 kB
Committed_AS: 592 kB
VmallocTotal: 67108864 kB
VmallocUsed: 760 kB
VmallocChunk: 0 kB
Percpu: 84 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
HugePages_Surp: 0
Hugepagesize: 2048 kB
Hugetlb: 0 kB
/ #
Cheers,
Prabhakar
Lad Prabhakar (10):
dt-bindings: soc: renesas: Move renesas.yaml from arm to soc
dt-bindings: riscv: Sort the CPU core list alphabetically
dt-bindings: riscv: Add Andes AX45MP core to the list
dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
riscv: boot: dts: r9a07g043: Add placeholder nodes
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
MAINTAINERS: Add entry for Renesas RISC-V architecture
RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC
.../devicetree/bindings/riscv/cpus.yaml | 11 +-
.../{arm => soc/renesas}/renesas.yaml | 3 +-
MAINTAINERS | 4 +-
arch/riscv/Kconfig.socs | 14 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 +
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 297 ++++++++++++++++++
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 42 +++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 56 ++++
arch/riscv/configs/defconfig | 2 +
11 files changed, 451 insertions(+), 8 deletions(-)
rename Documentation/devicetree/bindings/{arm => soc/renesas}/renesas.yaml (99%)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
--
2.25.1
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