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Message-ID: <9614efe9-d95e-fa0c-05fe-bac3fe62fa86@microchip.com>
Date: Thu, 15 Sep 2022 18:45:47 +0000
From: <Conor.Dooley@...rochip.com>
To: <daniel.lezcano@...aro.org>, <tglx@...utronix.de>,
<maz@...nel.org>, <palmer@...belt.com>
CC: <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<anup@...infault.org>, <Conor.Dooley@...rochip.com>,
<guoren@...nel.org>, <sagar.kadam@...ive.com>, <jrtc27@...c27.com>,
<aou@...s.berkeley.edu>, <ajones@...tanamicro.com>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <qemu-riscv@...gnu.org>,
<paul.walmsley@...ive.com>
Subject: Re: [PATCH v4 0/4] Fix dt-validate issues on qemu dtbdumps due to
dt-bindings
On 23/08/2022 19:33, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
>
> The device trees produced automatically for the virt and spike machines
> fail dt-validate on several grounds. Some of these need to be fixed in
> the linux kernel's dt-bindings, but others are caused by bugs in QEMU.
>
> Patches been sent that fix the QEMU issues [0], but a couple of them
> need to be fixed in the kernel's dt-bindings. The first patches add
> compatibles for "riscv,{clint,plic}0" which are present in drivers and
> the auto generated QEMU dtbs. The final patch should be ignored for all
> serious purposes unless you want to wash your eyes out afterwards, but
> JIC the versioned extensions ever come up, it's there.
Been no movement here for a few weeks, I assume things are waiting for
either Acks from Palmer or for him to take the patches directly?
Thanks,
Conor.
>
> Thanks to Rob Herring for reporting these issues [1],
> Conor.
>
> To reproduce the errors:
> ./build/qemu-system-riscv64 -nographic -machine virt,dumpdtb=qemu.dtb
> dt-validate -p /path/to/linux/kernel/Documentation/devicetree/bindings/processed-schema.json qemu.dtb
> (The processed schema needs to be generated first)
>
> 0 - https://lore.kernel.org/linux-riscv/20220810184612.157317-1-mail@conchuod.ie/
> 1 - https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
>
> Changes since v3:
> - dropped the charset restrictions for standard multiletter isa extensions
>
> Changes since v2:
> - removed the extra patches from the directory
>
> Changes since v1:
> - drop the "legacy systems" bit from the binding descriptions
> - convert to a regex for the isa string
>
> Conor Dooley (4):
> dt-bindings: timer: sifive,clint: add legacy riscv compatible
> dt-bindings: interrupt-controller: sifive,plic: add legacy riscv
> compatible
> dt-bindings: riscv: add new riscv,isa strings for emulators
> dt-bindings: riscv: isa string bonus content
>
> .../sifive,plic-1.0.0.yaml | 5 +++++
> .../devicetree/bindings/riscv/cpus.yaml | 9 ++++++---
> .../bindings/timer/sifive,clint.yaml | 18 ++++++++++++------
> 3 files changed, 23 insertions(+), 9 deletions(-)
>
>
> base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868
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