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Message-ID: <3693a3a1-5a2a-4cc5-fb55-f6ad9a4b3f72@microchip.com>
Date: Thu, 15 Sep 2022 21:36:02 +0000
From: <Conor.Dooley@...rochip.com>
To: <prabhakar.csengg@...il.com>, <geert+renesas@...der.be>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<paul.walmsley@...ive.com>, <palmer@...belt.com>,
<aou@...s.berkeley.edu>
CC: <heiko@...ech.de>, <atishp@...osinc.com>,
<devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
<linux-renesas-soc@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <biju.das.jz@...renesas.com>,
<prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v3 07/10] riscv: boot: dts: r9a07g043: Add placeholder
nodes
On 15/09/2022 19:15, Prabhakar wrote:
> riscv: boot: dts: r9a07g043: Add placeholder nodes
nit: s/boot//
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
Can you explain why do you need placeholder nodes for this and
cannot just directly include the other dtsis?
>
> This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier
> board DTS/I.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> v1->v3
> * New patch
> ---
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 177 +++++++++++++++++++++
> 1 file changed, 177 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> index fb6733f3cc2b..6d9db759a847 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -13,6 +13,14 @@ / {
> #address-cells = <2>;
> #size-cells = <2>;
>
> + audio_clk1: audio1-clk {
> + /* placeholder */
> + };
> +
> + audio_clk2: audio2-clk {
> + /* placeholder */
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -54,6 +62,23 @@ soc: soc {
> #size-cells = <2>;
> ranges;
>
> + ssi1: ssi@...4a000 {
> + reg = <0 0x1004a000 0 0x400>;
> + #sound-dai-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + spi1: spi@...4b000 {
> + reg = <0 0x1004b000 0 0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> scif0: serial@...4b800 {
> compatible = "renesas,scif-r9a07g043",
> "renesas,scif-r9a07g044";
> @@ -73,6 +98,48 @@ scif0: serial@...4b800 {
> status = "disabled";
> };
>
> + canfd: can@...50000 {
> + reg = <0 0x10050000 0 0x8000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + i2c0: i2c@...58000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x10058000 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + i2c1: i2c@...58400 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x10058400 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + adc: adc@...59000 {
> + reg = <0 0x10059000 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + sbc: spi@...60000 {
> + reg = <0 0x10060000 0 0x10000>,
> + <0 0x20000000 0 0x10000000>,
> + <0 0x10070000 0 0x10000>;
> + reg-names = "regs", "dirmap", "wbuf";
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> cpg: clock-controller@...10000 {
> compatible = "renesas,r9a07g043-cpg";
> reg = <0 0x11010000 0 0x10000>;
> @@ -104,6 +171,95 @@ pinctrl: pinctrl@...30000 {
> <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> };
>
> + sdhi0: mmc@...00000 {
> + reg = <0x0 0x11c00000 0 0x10000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + sdhi1: mmc@...10000 {
> + reg = <0x0 0x11c10000 0 0x10000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + eth0: ethernet@...20000 {
> + reg = <0 0x11c20000 0 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + eth1: ethernet@...30000 {
> + reg = <0 0x11c30000 0 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + phyrst: usbphy-ctrl@...40000 {
> + reg = <0 0x11c40000 0 0x10000>;
> + #reset-cells = <1>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ohci0: usb@...50000 {
> + reg = <0 0x11c50000 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ohci1: usb@...70000 {
> + reg = <0 0x11c70000 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ehci0: usb@...50100 {
> + reg = <0 0x11c50100 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ehci1: usb@...70100 {
> + reg = <0 0x11c70100 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + usb2_phy0: usb-phy@...50200 {
> + reg = <0 0x11c50200 0 0x700>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + usb2_phy1: usb-phy@...70200 {
> + reg = <0 0x11c70200 0 0x700>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + hsusb: usb@...60000 {
> + reg = <0 0x11c60000 0 0x10000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> plic: interrupt-controller@...00000 {
> compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> #interrupt-cells = <2>;
> @@ -116,5 +272,26 @@ plic: interrupt-controller@...00000 {
> resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> };
> +
> + wdt0: watchdog@...00800 {
> + reg = <0 0x12800800 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ostm1: timer@...01400 {
> + reg = <0x0 0x12801400 0x0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ostm2: timer@...01800 {
> + reg = <0x0 0x12801800 0x0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> };
> };
> --
> 2.25.1
>
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