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Message-Id: <20220915233432.31660-4-leoyang.li@nxp.com>
Date: Thu, 15 Sep 2022 18:34:26 -0500
From: Li Yang <leoyang.li@....com>
To: shawnguo@...nel.org, devicetree@...r.kernel.org
Cc: robh+dt@...nel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, Hou Zhiqiang <Zhiqiang.Hou@....com>,
Li Yang <leoyang.li@....com>
Subject: [PATCH v2 3/9] arm64: dts: ls1046a: Add big-endian property for PCIe nodes
From: Hou Zhiqiang <Zhiqiang.Hou@....com>
Add the big-endian property for LS1046A PCIe RC nodes.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
Signed-off-by: Li Yang <leoyang.li@....com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 8002d83b341b..a0619a45f3b8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -805,6 +805,7 @@ pcie1: pcie@...0000 {
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -844,6 +845,7 @@ pcie2: pcie@...0000 {
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -883,6 +885,7 @@ pcie3: pcie@...0000 {
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
--
2.37.1
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