linux-kernel - Re: [PATCH v1 1/3] dts: add Nuvoton sgpio feature

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Message-ID: <CAKUZ0+HLAxLw8Tio1HZt8TkYag_UGuDktjNbORwPzfRRrEJ0jQ@mail.gmail.com>
Date:   Thu, 15 Sep 2022 11:36:09 +0800
From:   Jim Liu <jim.t90615@...il.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Cc:     JJLIU0@...oton.com, KWLIU@...oton.com, linus.walleij@...aro.org,
        brgl@...ev.pl, robh+dt@...nel.org, avifishman70@...il.com,
        tmaimon77@...il.com, tali.perry1@...il.com, venture@...gle.com,
        yuenn@...gle.com, benjaminfair@...gle.com, CTCCHIEN@...oton.com,
        linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, openbmc@...ts.ozlabs.org
Subject: Re: [PATCH v1 1/3] dts: add Nuvoton sgpio feature

Hi Krzysztof Kozlowski

Thanks for your review.
I am modifying this driver now, and i have some questions.

what's mean "Generic node name." ?
Nuvoton NPCM750 SGPIO module is base on serial to parallel IC (HC595)
and parallel to serial IC (HC165).
and dts node name is followed aspeed dts node name.

Could you give more information??

Best regards,
Jim

On Fri, Mar 11, 2022 at 5:18 PM Krzysztof Kozlowski
<krzysztof.kozlowski@...onical.com> wrote:
>
> On 11/03/2022 07:09, jimliu2 wrote:
> > add Nuvoton sgpio feature
> >
> > Signed-off-by: jimliu2 <JJLIU0@...oton.com>
> > ---
> >  arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 30 +++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> > index 3696980a3da1..58f4b463c745 100644
> > --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> > +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> > @@ -329,6 +329,36 @@
> >                               status = "disabled";
> >                       };
> >
> > +                     sgpio1: sgpio@...000 {
>
> Generic node name.
>
> > +                             clocks = <&clk NPCM7XX_CLK_APB3>;
> > +                             compatible = "nuvoton,npcm750-sgpio";
> > +                             interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             pinctrl-names = "default";
> > +                             pinctrl-0 = <&iox1_pins>;
> > +                             bus-frequency = <16000000>;
> > +                             nin_gpios = <64>;
> > +                             nout_gpios = <64>;
> > +                             reg = <0x101000 0x200>;
>
> In each node first goes compatible, then reg.
>
> Best regards,
> Krzysztof