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Message-ID: <20220915075849.1920-3-rex-bc.chen@mediatek.com>
Date: Thu, 15 Sep 2022 15:58:47 +0800
From: Bo-Chen Chen <rex-bc.chen@...iatek.com>
To: <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>
CC: <matthias.bgg@...il.com>,
<angelogioacchino.delregno@...labora.com>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
Bo-Chen Chen <rex-bc.chen@...iatek.com>
Subject: [PATCH 2/4] arm64: dts: mt8195: Add dptx nodes
Add edptx and dptx nodes for MT8195.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 93e6a106a9b8..6f3f9bf3dc54 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1241,6 +1241,9 @@
reg = <0x189 0x2>;
bits = <7 5>;
};
+ dp_calibration: dp-data@1ac {
+ reg = <0x1ac 0x10>;
+ };
};
u3phy2: t-phy@...40000 {
@@ -2178,5 +2181,27 @@
clock-names = "engine", "pixel", "pll";
status = "disabled";
};
+
+ edp_tx: edp-tx@...00000 {
+ status = "disabled";
+ compatible = "mediatek,mt8195-edp-tx";
+ reg = <0 0x1c500000 0 0x8000>;
+ nvmem-cells = <&dp_calibration>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
+ interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+ max-linkrate-mhz = <8100>;
+ };
+
+ dp_tx: dp-tx@...00000 {
+ compatible = "mediatek,mt8195-dp-tx";
+ reg = <0 0x1c600000 0 0x8000>;
+ nvmem-cells = <&dp_calibration>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
+ interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ max-linkrate-mhz = <8100>;
+ };
};
};
--
2.18.0
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