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Message-ID: <BN9PR11MB5276F03A090073F388B824488C499@BN9PR11MB5276.namprd11.prod.outlook.com>
Date:   Thu, 15 Sep 2022 09:39:30 +0000
From:   "Tian, Kevin" <kevin.tian@...el.com>
To:     Lu Baolu <baolu.lu@...ux.intel.com>,
        "iommu@...ts.linux.dev" <iommu@...ts.linux.dev>
CC:     Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
        "Robin Murphy" <robin.murphy@....com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 1/1] iommu/vt-d: Decouple PASID & PRI enabling from SVA

> From: Lu Baolu <baolu.lu@...ux.intel.com>
> Sent: Thursday, September 15, 2022 4:58 PM
> 
> Previously the PCI PASID and PRI capabilities are enabled in the path of
> iommu device probe only if INTEL_IOMMU_SVM is configured and the device
> supports ATS. As we've already decoupled the I/O page fault handler from
> SVA, we could also decouple PASID and PRI enabling from it to make room
> for growth of new features like kernel DMA with PASID, SIOV and nested
> translation.
> 
> At the same time, the iommu_enable_dev_iotlb() helper is also called in
> iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA) path. It's
> unnecessary
> and duplicate. This cleanups this helper to make the code neat.
> 
> Signed-off-by: Lu Baolu <baolu.lu@...ux.intel.com>

Reviewed-by: Kevin Tian <kevin.tian@...el.com>

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