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Date:   Thu, 15 Sep 2022 14:30:44 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Choong Yong Liang <yong.liang.choong@...ux.intel.com>
Cc:     "David S . Miller" <davem@...emloft.net>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>, Dan Murphy <dmurphy@...com>,
        Song Yoong Siang <yoong.siang.song@...el.com>,
        Cacho Gerome <g-cacho@...com>, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH net 1/1] net: phy: dp83867: perform phy reset after
 modifying auto-neg setting

On Thu, Sep 15, 2022 at 05:02:58AM -0400, Choong Yong Liang wrote:
> From: Song Yoong Siang <yoong.siang.song@...el.com>
> 
> In the case where TI DP83867 is connected back-to-back with another TI
> DP83867, SEEDs match will occurs when advertised link speed is changed from
> 100 Mbps to 1 Gbps, which causing Master/Slave resolution fails and restart
> of the auto-negotiation. As a result, TI DP83867 copper auto-negotiation
> completion will takes up to 15 minutes.

802.3 seems to indicate that if the seeds match, it should immediately
generate a new random seed and try the master/slave selection
again. So you seem to be saying this part is broken.

> To resolve the issue, this patch implemented phy reset (software restart
> which perform a full reset, but not including registers) immediately after
> modifying auto-negotiation setting. By applying reset to the phy, it would
> also reset the lfsr which would increase the probability of SEEDS being
> different and help in Master/Slave resolution.

So this just increases the likelihood of different seed values. The 15
minute wait could still happen. The link peer seed value should be
accessible via the autoneg page registers. Can the local seed value be
determined? Linux can then detect that the same seed is being used and
give the PHY a kick to pick a new seed.

Is there anything useful in register 10 bit, 15?

So long as you don't use interrupts, phylib is going to poll the PHY
once per second. It seems like you can get a better workaround by
using that polling to check if the PHY as got stuck, and give it a
kick.

	Andrew

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