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Message-ID: <CAL_Jsq+u5ZjCNbxQd9FfgvHx6BM4AYjMS63qmm22k2zn5Xqtyg@mail.gmail.com>
Date: Fri, 16 Sep 2022 07:03:55 -0500
From: Rob Herring <robh@...nel.org>
To: Janne Grunau <j@...nau.net>
Cc: iommu@...ts.linux.dev,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
asahi@...ts.linux.dev, Sven Peter <sven@...npeter.dev>,
Alyssa Rosenzweig <alyssa@...enzweig.io>,
Hector Martin <marcan@...can.st>,
Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
Linux IOMMU <iommu@...ts.linux-foundation.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 4/5] iommu/io-pgtable-dart: Add DART PTE support for t6000
On Fri, Sep 16, 2022 at 4:42 AM Janne Grunau <j@...nau.net> wrote:
>
> From: Sven Peter <sven@...npeter.dev>
>
> The DARTs present in the M1 Pro/Max/Ultra SoC use a diffent PTE format.
> They support a 42bit physical address space by shifting the paddr and
> extending its mask inside the PTE.
> They also come with mandatory sub-page protection now which we just
> configure to always allow access to the entire page. This feature is
> already present but optional on the previous DARTs which allows to
> unconditionally configure it.
>
> Signed-off-by: Sven Peter <sven@...npeter.dev>
> Co-developed-by: Janne Grunau <j@...nau.net>
> Signed-off-by: Janne Grunau <j@...nau.net>
>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - apply change to io-pgtable-dart.c
> - handle pte <> paddr conversion based on the pte format instead of
> the output address size
>
> Changes in v2:
> - add APPLE_DART2 PTE format
>
> drivers/iommu/io-pgtable-dart.c | 49 ++++++++++++++++++++++++++++-----
> drivers/iommu/io-pgtable.c | 1 +
> include/linux/io-pgtable.h | 1 +
> 3 files changed, 44 insertions(+), 7 deletions(-)
Reviewed-by: Rob Herring <robh@...nel.org>
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