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Message-ID: <5097a283-6111-bedc-13c6-61a581f8b72c@redhat.com>
Date: Sat, 17 Sep 2022 13:42:13 +0200
From: Hans de Goede <hdegoede@...hat.com>
To: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
"H. Peter Anvin" <hpa@...or.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Pavel Machek <pavel@....cz>,
Andrew Cooper <Andrew.Cooper3@...rix.com>
Cc: linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
antonio.gomez.iglesias@...ux.intel.com
Subject: Re: [PATCH 0/3] Check enumeration before MSR save/restore
Hi,
On 9/13/22 02:50, Pawan Gupta wrote:
> On Mon, Sep 12, 2022 at 04:38:44PM -0700, Pawan Gupta wrote:
>> Hi,
>>
>> This patchset is to fix the "unchecked MSR access error" [1] during S3
>> resume. Patch 1/3 adds a feature bit for MSR_IA32_TSX_CTRL.
>>
>> Patch 2/3 adds a feature bit for MSR_AMD64_LS_CFG.
>>
>> Patch 3/3 adds check for feature bit before adding any speculation
>> control MSR to the list of MSRs to save/restore.
>>
>> [1] https://lore.kernel.org/lkml/20220906201743.436091-1-hdegoede@redhat.com/
>
> Added the correct email-id of Hans de Goede <hdegoede@...hat.com>.
I have tested this series and I can confirm that it fixes the exception
which I was seeing on a Packard Bell Dot SC with an Atom N2600 CPU:
Tested-by: Hans de Goede <hdegoede@...hat.com>
Regards,
Hans
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