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Message-Id: <20220919175721.354679-7-yung-chuan.liao@linux.intel.com>
Date: Tue, 20 Sep 2022 01:57:16 +0800
From: Bard Liao <yung-chuan.liao@...ux.intel.com>
To: alsa-devel@...a-project.org, vkoul@...nel.org
Cc: vinod.koul@...aro.org, linux-kernel@...r.kernel.org,
pierre-louis.bossart@...ux.intel.com, bard.liao@...el.com
Subject: [PATCH 06/11] soundwire: intel: move shim initialization before power up/down
From: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
Move code around before additional simplification. No functionality
change.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
Reviewed-by: Rander Wang <rander.wang@...el.com>
Signed-off-by: Bard Liao <yung-chuan.liao@...ux.intel.com>
---
drivers/soundwire/intel.c | 231 +++++++++++++++++++-------------------
1 file changed, 115 insertions(+), 116 deletions(-)
diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
index 2d828d98e153..140cf36eb407 100644
--- a/drivers/soundwire/intel.c
+++ b/drivers/soundwire/intel.c
@@ -260,6 +260,121 @@ static void intel_debugfs_exit(struct sdw_intel *sdw) {}
/*
* shim ops
*/
+/* this needs to be called with shim_lock */
+static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
+{
+ void __iomem *shim = sdw->link_res->shim;
+ unsigned int link_id = sdw->instance;
+ u16 ioctl;
+
+ /* Switch to MIP from Glue logic */
+ ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
+
+ ioctl &= ~(SDW_SHIM_IOCTL_DOE);
+ intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
+ usleep_range(10, 15);
+
+ ioctl &= ~(SDW_SHIM_IOCTL_DO);
+ intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
+ usleep_range(10, 15);
+
+ ioctl |= (SDW_SHIM_IOCTL_MIF);
+ intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
+ usleep_range(10, 15);
+
+ ioctl &= ~(SDW_SHIM_IOCTL_BKE);
+ ioctl &= ~(SDW_SHIM_IOCTL_COE);
+ intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
+ usleep_range(10, 15);
+
+ /* at this point Master IP has full control of the I/Os */
+}
+
+/* this needs to be called with shim_lock */
+static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
+{
+ unsigned int link_id = sdw->instance;
+ void __iomem *shim = sdw->link_res->shim;
+ u16 ioctl;
+
+ /* Glue logic */
+ ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
+ ioctl |= SDW_SHIM_IOCTL_BKE;
+ ioctl |= SDW_SHIM_IOCTL_COE;
+ intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
+ usleep_range(10, 15);
+
+ ioctl &= ~(SDW_SHIM_IOCTL_MIF);
+ intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
+ usleep_range(10, 15);
+
+ /* at this point Integration Glue has full control of the I/Os */
+}
+
+static int intel_shim_init(struct sdw_intel *sdw)
+{
+ void __iomem *shim = sdw->link_res->shim;
+ unsigned int link_id = sdw->instance;
+ int ret = 0;
+ u16 ioctl = 0, act = 0;
+
+ mutex_lock(sdw->link_res->shim_lock);
+
+ /* Initialize Shim */
+ ioctl |= SDW_SHIM_IOCTL_BKE;
+ intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
+ usleep_range(10, 15);
+
+ ioctl |= SDW_SHIM_IOCTL_WPDD;
+ intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
+ usleep_range(10, 15);
+
+ ioctl |= SDW_SHIM_IOCTL_DO;
+ intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
+ usleep_range(10, 15);
+
+ ioctl |= SDW_SHIM_IOCTL_DOE;
+ intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
+ usleep_range(10, 15);
+
+ intel_shim_glue_to_master_ip(sdw);
+
+ u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);
+ act |= SDW_SHIM_CTMCTL_DACTQE;
+ act |= SDW_SHIM_CTMCTL_DODS;
+ intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
+ usleep_range(10, 15);
+
+ mutex_unlock(sdw->link_res->shim_lock);
+
+ return ret;
+}
+
+static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
+{
+ void __iomem *shim = sdw->link_res->shim;
+ unsigned int link_id = sdw->instance;
+ u16 wake_en, wake_sts;
+
+ mutex_lock(sdw->link_res->shim_lock);
+ wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
+
+ if (wake_enable) {
+ /* Enable the wakeup */
+ wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
+ intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
+ } else {
+ /* Disable the wake up interrupt */
+ wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
+ intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
+
+ /* Clear wake status */
+ wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
+ wake_sts |= (SDW_SHIM_WAKESTS_STATUS << link_id);
+ intel_writew(shim, SDW_SHIM_WAKESTS, wake_sts);
+ }
+ mutex_unlock(sdw->link_res->shim_lock);
+}
static int intel_link_power_up(struct sdw_intel *sdw)
{
@@ -340,122 +455,6 @@ static int intel_link_power_up(struct sdw_intel *sdw)
return ret;
}
-/* this needs to be called with shim_lock */
-static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
-{
- void __iomem *shim = sdw->link_res->shim;
- unsigned int link_id = sdw->instance;
- u16 ioctl;
-
- /* Switch to MIP from Glue logic */
- ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
-
- ioctl &= ~(SDW_SHIM_IOCTL_DOE);
- intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
- usleep_range(10, 15);
-
- ioctl &= ~(SDW_SHIM_IOCTL_DO);
- intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
- usleep_range(10, 15);
-
- ioctl |= (SDW_SHIM_IOCTL_MIF);
- intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
- usleep_range(10, 15);
-
- ioctl &= ~(SDW_SHIM_IOCTL_BKE);
- ioctl &= ~(SDW_SHIM_IOCTL_COE);
- intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
- usleep_range(10, 15);
-
- /* at this point Master IP has full control of the I/Os */
-}
-
-/* this needs to be called with shim_lock */
-static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
-{
- unsigned int link_id = sdw->instance;
- void __iomem *shim = sdw->link_res->shim;
- u16 ioctl;
-
- /* Glue logic */
- ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
- ioctl |= SDW_SHIM_IOCTL_BKE;
- ioctl |= SDW_SHIM_IOCTL_COE;
- intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
- usleep_range(10, 15);
-
- ioctl &= ~(SDW_SHIM_IOCTL_MIF);
- intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
- usleep_range(10, 15);
-
- /* at this point Integration Glue has full control of the I/Os */
-}
-
-static int intel_shim_init(struct sdw_intel *sdw)
-{
- void __iomem *shim = sdw->link_res->shim;
- unsigned int link_id = sdw->instance;
- int ret = 0;
- u16 ioctl = 0, act = 0;
-
- mutex_lock(sdw->link_res->shim_lock);
-
- /* Initialize Shim */
- ioctl |= SDW_SHIM_IOCTL_BKE;
- intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
- usleep_range(10, 15);
-
- ioctl |= SDW_SHIM_IOCTL_WPDD;
- intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
- usleep_range(10, 15);
-
- ioctl |= SDW_SHIM_IOCTL_DO;
- intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
- usleep_range(10, 15);
-
- ioctl |= SDW_SHIM_IOCTL_DOE;
- intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
- usleep_range(10, 15);
-
- intel_shim_glue_to_master_ip(sdw);
-
- u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);
- act |= SDW_SHIM_CTMCTL_DACTQE;
- act |= SDW_SHIM_CTMCTL_DODS;
- intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
- usleep_range(10, 15);
-
- mutex_unlock(sdw->link_res->shim_lock);
-
- return ret;
-}
-
-static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
-{
- void __iomem *shim = sdw->link_res->shim;
- unsigned int link_id = sdw->instance;
- u16 wake_en, wake_sts;
-
- mutex_lock(sdw->link_res->shim_lock);
- wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
-
- if (wake_enable) {
- /* Enable the wakeup */
- wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
- intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
- } else {
- /* Disable the wake up interrupt */
- wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
- intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
-
- /* Clear wake status */
- wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
- wake_sts |= (SDW_SHIM_WAKESTS_STATUS << link_id);
- intel_writew(shim, SDW_SHIM_WAKESTS, wake_sts);
- }
- mutex_unlock(sdw->link_res->shim_lock);
-}
-
static int intel_link_power_down(struct sdw_intel *sdw)
{
u32 link_control, spa_mask, cpa_mask;
--
2.25.1
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