[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20220919183342.4090-1-vidyas@nvidia.com>
Date: Tue, 20 Sep 2022 00:03:39 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: <jingoohan1@...il.com>, <gustavo.pimentel@...opsys.com>,
<lpieralisi@...nel.org>, <robh@...nel.org>, <kw@...ux.com>,
<bhelgaas@...gle.com>, <mani@...nel.org>,
<Sergey.Semin@...kalelectronics.ru>, <dmitry.baryshkov@...aro.org>,
<linmq006@...il.com>, <ffclaire1224@...il.com>
CC: <thierry.reding@...il.com>, <jonathanh@...dia.com>,
<linux-pci@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <kthota@...dia.com>,
<mmaddireddy@...dia.com>, <vidyas@...dia.com>, <sagar.tv@...il.com>
Subject: [PATCH V4 0/3] PCI: designware-ep: Fix DBI access before core init
This series attempts to fix the issue with core register (Ex:- DBI) accesses
causing system hang issues in platforms where there is a dependency on the
availability of PCIe Reference clock from the host for their core
initialization.
This series is verified on Tegra194 & Tegra234 platforms.
Manivannan, could you please verify on qcom platforms?
V4:
* Addressed review comments from Bjorn and Manivannan
* Added .ep_init_late() ops
* Added patches to refactor code in qcom and tegra platforms
Vidya Sagar (3):
PCI: designware-ep: Fix DBI access before core init
PCI: qcom-ep: Refactor EP initialization completion
PCI: tegra194: Refactor EP initialization completion
.../pci/controller/dwc/pcie-designware-ep.c | 112 ++++++++++--------
drivers/pci/controller/dwc/pcie-designware.h | 10 +-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 +++--
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
4 files changed, 85 insertions(+), 68 deletions(-)
--
2.17.1
Powered by blists - more mailing lists