linux-kernel - Re: [PATCH v2 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation

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Message-ID: <3981e6e8-d4bb-b13d-7aaa-7aea83ffaad9@linaro.org>
Date:   Mon, 19 Sep 2022 08:56:11 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Tomer Maimon <tmaimon77@...il.com>, Rob Herring <robh@...nel.org>
Cc:     Avi Fishman <avifishman70@...il.com>,
        Tali Perry <tali.perry1@...il.com>,
        Joel Stanley <joel@....id.au>,
        Patrick Venture <venture@...gle.com>,
        Nancy Yuen <yuenn@...gle.com>,
        Benjamin Fair <benjaminfair@...gle.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Jonathan Neuschäfer <j.neuschaefer@....net>,
        zhengbin13@...wei.com, OpenBMC Maillist <openbmc@...ts.ozlabs.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO
 documentation

On 18/09/2022 20:28, Tomer Maimon wrote:
> Hi Rob,
> 
> Thanks for your comment and sorry for the late reply.

Two months... we are out of the context and this will not help your
patchset.

> 
> On Tue, 19 Jul 2022 at 00:10, Rob Herring <robh@...nel.org> wrote:
>>

(...)

>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +    #include <dt-bindings/gpio/gpio.h>
>>> +
>>> +    soc {
>>> +      #address-cells = <2>;
>>> +      #size-cells = <2>;
>>> +
>>> +      pinctrl: pinctrl@...00000 {
>>> +        compatible = "nuvoton,npcm845-pinctrl";
>>> +        ranges = <0x0 0x0 0xf0010000 0x8000>;
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +        nuvoton,sysgcr = <&gcr>;
>>> +
>>> +        gpio0: gpio@...10000 {
>>
>> gpio@0
>>
>> Is this really a child block of the pinctrl? Doesn't really look like it
>> based on addressess. Where are the pinctrl registers? In the sysgcr? If
>> so, then pinctrl should be a child of it. But that doesn't really work
>> too well with gpio child nodes...
> the pin controller mux is handled by sysgcr this is why the sysgcr in
> the mother node,
> and the pin configuration are handled by the GPIO registers.  each
> GPIO bank (child) contains 32 GPIO.
> this is why the GPIO is the child node.

Then maybe pinctrl should be the sysgcr and expose regmap for other devices?


Best regards,
Krzysztof