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Message-ID: <Yyhyxmt+rhxEI0VH@smile.fi.intel.com>
Date: Mon, 19 Sep 2022 16:46:46 +0300
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Cc: Lennert Buytenhek <buytenh@...tstofly.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>,
linux-serial <linux-serial@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: I/O page faults from 8250_mid PCIe UART after TIOCVHANGUP
On Thu, Sep 15, 2022 at 07:27:45PM +0300, Ilpo Järvinen wrote:
> On Wed, 14 Sep 2022, Andy Shevchenko wrote:
> > On Wed, Sep 14, 2022 at 02:10:44PM +0300, Lennert Buytenhek wrote:
> > > On Wed, Sep 14, 2022 at 01:09:40PM +0300, Andy Shevchenko wrote:
...
> - /*
> - * The above check will only give an accurate result the first time
> - * the port is opened so this value needs to be preserved.
> - */
Side note: I haven't got why you removed this comment (it may be some staled
info, but shouldn't be done in the separate change then?).
--
With Best Regards,
Andy Shevchenko
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