| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Mon, 19 Sep 2022 19:44:54 +0530
From: Sandipan Patra <spatra@...dia.com>
To: <thierry.reding@...il.com>, <jonathanh@...dia.com>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <bbasu@...dia.com>, <kyarlagadda@...dia.com>,
Sandipan Patra <spatra@...dia.com>
Subject: [PATCH v5 2/3] arm64: tegra: Add PWM controllers on Tegra234
Tegra234 has eight single-channel PWM controllers, one of them in the
AON block.
Signed-off-by: Sandipan Patra <spatra@...dia.com>
---
V4->V5: Update compatable with Tegra234 and fallback
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 88 +++++++++++++++++++++++-
1 file changed, 86 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 0170bfa8a467..b1b29e3c207c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -870,8 +870,8 @@
};
pwm1: pwm@...0000 {
- compatible = "nvidia,tegra194-pwm",
- "nvidia,tegra186-pwm";
+ compatible = "nvidia,tegra234-pwm",
+ "nvidia,tegra194-pwm";
reg = <0x3280000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM1>;
clock-names = "pwm";
@@ -881,6 +881,90 @@
#pwm-cells = <2>;
};
+ pwm2: pwm@...0000 {
+ compatible = "nvidia,tegra234-pwm",
+ "nvidia,tegra194-pwm";
+ reg = <0x3290000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM2>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM2>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm3: pwm@...0000 {
+ compatible = "nvidia,tegra234-pwm",
+ "nvidia,tegra194-pwm";
+ reg = <0x32a0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM3>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM3>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm4: pwm@...0000 {
+ compatible = "nvidia,tegra234-pwm",
+ "nvidia,tegra194-pwm";
+ reg = <0xc340000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM4>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM4>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm5: pwm@...0000 {
+ compatible = "nvidia,tegra234-pwm",
+ "nvidia,tegra194-pwm";
+ reg = <0x32c0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM5>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM5>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm6: pwm@...0000 {
+ compatible = "nvidia,tegra234-pwm",
+ "nvidia,tegra194-pwm";
+ reg = <0x32d0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM6>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM6>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm7: pwm@...0000 {
+ compatible = "nvidia,tegra234-pwm",
+ "nvidia,tegra194-pwm";
+ reg = <0x32e0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM7>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM7>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm8: pwm@...0000 {
+ compatible = "nvidia,tegra234-pwm",
+ "nvidia,tegra194-pwm";
+ reg = <0x32f0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM8>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM8>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
spi@...0000 {
compatible = "nvidia,tegra234-qspi";
reg = <0x3300000 0x1000>;
--
2.17.1
Powered by blists - more mailing lists